/**
  ******************************************************************************
             Copyright(c) 2022 China Core Co. Ltd.
                      All Rights Reserved
  ******************************************************************************
  * @file    ccm4101_reg.h
  * @author  Product application department
  * @version V1.0
  * @date    2023.10.20
  * @brief   Header file of chip reg
  *
  ******************************************************************************
*/

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __CCM4101_REG_H
#define __CCM4101_REG_H

#ifdef __cplusplus
extern "C"
{
#endif

/* Includes ------------------------------------------------------------------*/
#include "iomacros.h"

/******************************Macros Definition********************************/
/**
 * @brief 4101 Module Base Address Definition
 */
#define __BASE_ADDR__
#ifdef __BASE_ADDR__

/* M4 peripheral module base address definition*/
#define SPIM1_BASE_ADDR     (0x13000000)    /*!< SSI1 base address */
#define TRNG_BASE_ADDR      (0x14000000)    /**< TRNG base address */
#define IOCTRL_BASE_ADDR 	  (0x40000000)   	/**< IOCTRL base address */
#define CCM_BASE_ADDR 		  (0x40001000)    /**< CCM base address */
#define RESET_BASE_ADDR 	  (0x40002000)    /**< RESET base address */
#define OTP_BASE_ADDR 		  (0X40003000)    /**< OTP base address */
#define CPM_BASE_ADDR 		  (0x40004000)    /**< CPM base address */
#define WDT_BASE_ADDR 		  (0x40005000)    /**< WDT base address */
#define TC_BASE_ADDR        (0x40006000)    /**< TC base address */
#define PIT1_BASE_ADDR 		  (0x40007000)    /**< PIT32_1 32bits base address */
#define PIT2_BASE_ADDR 		  (0x40008000)    /**< PIT32_2 32bits base address */
#define EDMAC1_0_BASE_ADDR 	(0X4000A000) 	  /**< EDMAC1_0 base address */
#define EDMAC1_1_BASE_ADDR 	(0X4000A040) 	  /**< EDMAC1_1 base address */
#define SPI1_BASE_ADDR 		  (0x40010000)    /**< SPI1 base address*/
#define SPI2_BASE_ADDR 		  (0x40011000)    /**< SPI2 base address */
#define SPI3_BASE_ADDR 		  (0x40012000)    /**< SPI3 base address*/
#define UART1_BASE_ADDR 	  (0x40013000)    /**< UART1 base address*/
#define UART2_BASE_ADDR 	  (0x40014000)    /**< UART2 base address*/
#define I2C1_BASE_ADDR 		  (0x40017000)    /**< I2C1 base address*/
#define PWM_BASE_ADDR 		  (0x40018000)    /**< PWM base address */
#define EPORT0_BASE_ADDR 	  (0x40019000)   	/**< EPORT0 base address*/
#define EPORT1_BASE_ADDR 	  (0x4001A000)   	/**< EPORT1 base address*/
#define UART3_BASE_ADDR 	  (0x4001D000)    /**< UART3 base address*/
#define ADC_BASE_ADDR       (0x40020000)    /**< ADC base address*/
#define EPORT2_BASE_ADDR    (0x40024000)    /**< EPORT2 base address*/
#define EPORT5_BASE_ADDR    (0x40027000)    /**< EPORT5 base address*/
#define EPORT6_BASE_ADDR    (0x40028000)    /**< EPORT6 base address*/
#define EPORT7_BASE_ADDR    (0x40029000)    /**< EPORT7 base address*/
#define PWMT1_BASE_ADDR     (0x4002d000)    /**< PWMT1 base address*/
#define PWMT2_BASE_ADDR     (0x4002e000)    /**< PWMT2 base address*/
#define SECDET_BASE_ADDR    (0X40033000)    /**< SECDET base address*/
#define AES_BASE_ADDR       (0x40041000)    /**< AES base address*/
#define CRC1_BASE_ADDR      (0x40045000)    /**< CRC1 base address */
#define DMAC1_BASE_ADDR     (0x40046000)    /**< DMA1 base address*/
#define DMAC2_BASE_ADDR     (0x40047000)    /**< DMA2 base address*/
#define ICACHE_BASE_ADDR    (0x40051000)    /**< ICACHE base address*/
#define DCACHE_BASE_ADDR    (0x40055000)    /**< DCACHE base address*/
#define M4SYS_BASE_ADDR     (0xE0000000)    /**< M4 base address */

#endif
/**
 * @brief 
 */
#define __MODULE___
#ifdef __MODULE___

#define SSI1         ((SSI_TypeDef *)(SPIM1_BASE_ADDR))
#define IOCTRL       ((IOCTRL_TypeDef *)(IOCTRL_BASE_ADDR))
#define CCM          ((CCM_TypeDef *)(CCM_BASE_ADDR))
#define RST          ((RESET_TypeDef *)(RESET_BASE_ADDR))
#define OTP          ((OTP_TypeDef *)(OTP_BASE_ADDR))
#define CPM          ((CPM_TypeDef *)(CPM_BASE_ADDR))
#define WDT          ((WDT_TypeDef *)(WDT_BASE_ADDR))
#define TC           ((TC_TypeDef *)(TC_BASE_ADDR))
#define PIT1         ((PIT32_TypeDef *)(PIT1_BASE_ADDR))
#define PIT2         ((PIT32_TypeDef *)(PIT2_BASE_ADDR))
#define EDMAC1_0     ((EDMAC_TypeDef *)(EDMAC1_0_BASE_ADDR))
#define EDMAC1_1     ((EDMAC_TypeDef *)(EDMAC1_1_BASE_ADDR))
#define SPI1         ((SPI_TypeDef *)(SPI1_BASE_ADDR))
#define SPI2         ((SPI_TypeDef *)(SPI2_BASE_ADDR))
#define SPI3         ((SPI_TypeDef *)(SPI3_BASE_ADDR))
#define UART1        ((UART_TypeDef *)UART1_BASE_ADDR)
#define UART2        ((UART_TypeDef *)UART2_BASE_ADDR)
#define I2C1         ((I2C_TypeDef *)(I2C1_BASE_ADDR))
#define PWM          ((PWM_TypeDef *)(PWM_BASE_ADDR))
#define EPORT0       ((EPORT_TypeDef *)(EPORT0_BASE_ADDR))
#define EPORT1       ((EPORT_TypeDef *)(EPORT1_BASE_ADDR))
#define UART3        ((UART_TypeDef *)(UART3_BASE_ADDR))
#define ADC          ((ADC_TypeDef *)(ADC_BASE_ADDR))
#define EPORT2       ((EPORT_TypeDef *)(EPORT2_BASE_ADDR))
#define EPORT5       ((EPORT_TypeDef *)(EPORT5_BASE_ADDR))
#define EPORT6       ((EPORT_TypeDef *)(EPORT6_BASE_ADDR))
#define EPORT7       ((EPORT_TypeDef *)(EPORT7_BASE_ADDR))
#define PWMT1        ((PWMT_TypeDef *)(PWMT1_BASE_ADDR))
#define PWMT2        ((PWMT_TypeDef *)(PWMT2_BASE_ADDR))
#define SECDET       ((SECDET_TypeDef *)(SECDET_BASE_ADDR))
#define TRNG         ((TRNG_TypeDef *)(TRNG_BASE_ADDR))
#define CRC1         ((CRC_TypeDef *) (CRC1_BASE_ADDR))
#define DMAC1        ((DMAC_TypeDef *)(DMAC1_BASE_ADDR))
#define DMAC2        ((DMAC_TypeDef *) (DMAC2_BASE_ADDR))
#define ICACHE       ((CACHE_TypeDef *)(ICACHE_BASE_ADDR))
#define DCACHE       ((CACHE_TypeDef *)(DCACHE_BASE_ADDR))

#endif

/**
 * @brief
 */
#define __MODULE_BIT__
#ifdef __MODULE_BIT__

#define __EPT__
#ifdef __EPT__
    /*** EPT **********************************************/
    /*** CSR ************/

#endif /* end __EPT__ */

#define __EIC__
#ifdef __EIC__
    /*** EIC **********************************************/
    /*** IER Interrupt Enable Register ************/

#endif /* end __EIC__ */

#define __ADC__
#ifdef __ADC__
/*** ADC **********************************************/
/*ADC interrupt and status register:ADC_ISR*/
#define ADC_ANALOG_WD_FLAG (((uint32_t)1 << 7))
#define ADC_FIFO_EMPTY_STATUS (((uint32_t)1 << 6))
#define ADC_FIFO_FULL_STATUS (((uint32_t)1 << 5))
#define ADC_OVER_RUN_FLAG (((uint32_t)1 << 4))
#define ADC_END_SEQUENCE_FLAG (((uint32_t)1 << 3))
#define ADC_END_CONVERSION_FLAG (((uint32_t)1 << 2))
#define ADC_END_SAMPLING_FLAG (((uint32_t)1 << 1))
#define ADC_READY_FLAG (((uint32_t)1 << 0))

/*ADC interrupt enable register:ADC_IER*/
#define ADC_ANALOG_WD_INT_EN (((uint32_t)1 << 7))
#define ADC_OVER_RUN_INT_EN (((uint32_t)1 << 4))
#define ADC_END_SEQUENCE_INT_EN (((uint32_t)1 << 3))
#define ADC_END_CONVERSION_INT_EN (((uint32_t)1 << 2))
#define ADC_END_SAMPLING_INT_EN (((uint32_t)1 << 1))
#define ADC_READY_INT_EN (((uint32_t)1 << 0))

/*ADC control register:ADC_CR*/
#define ADC_STOP_CONVERSION_CMD_EN (((uint32_t)1 << 3))
#define ADC_START_CONVERSION_CMD_EN (((uint32_t)1 << 2))
#define ADC_DISABLE_CMD_EN (((uint32_t)1 << 1))
#define ADC_ENABLE_CMD_EN (((uint32_t)1 << 0))

/*ADC configuration register 1:ADC_CFGR1*/
#define ADC_ANALOG_INPUT_DIFF_MASK (((uint32_t)1 << 31))
#define ADC_OVERRUN_MODE_MASK (((uint32_t)1 << 30))
#define ADC_QADC_CLK_DISABLE_MASK (((uint32_t)1 << 29))
#define ADC_SAMPLE_OUTPUT_BUFFER_EN (((uint32_t)1 << 28))
#define ADC_DISCONTINUOUS_EN (((uint32_t)1 << 23))
#define ADC_AUTO_OFF_MODE_EN (((uint32_t)1 << 22))
#define ADC_WAIT_CONVERSION_MODE_MASK (((uint32_t)1 << 21))
#define ADC_CONTINUOUS_CONVERSION_MASK (((uint32_t)1 << 20))
#define ADC_EXTERNAL_VREF_MASK (((uint32_t)1 << 15))
#define ADC_CFGR1_ALIGN_LEFT_ALIGNMENT (((uint32_t)1 << 10))
#define ADC_CFGR1_ALIGN_RIGHT_ALIGNMENT ((uint32_t)(0 << 10))
#define ADC_LEFT_ALIGNMENT_MASK (((uint32_t)1 << 10))
#define ADC_CFGR1_RES_10BIT (((uint32_t)1 << 8))
#define ADC_CFGR1_DMATH_2 ((uint32_t)(2 << 4))
#define ADC_DMA_ACCESS_EN (((uint32_t)1 << 0))
#define ADC_CFGR1_SEQ_LEN_SHIFT ((uint32_t)(24))

/*ADC configuration register 2:ADC_CFGR2*/
#define ADC_ANALOG_INPUT_BYPASS_EN (((uint32_t)1 << 15))
#define ADC_CFGR2_QPR_0 ((uint32_t)(0 << 8))
#define ADC_CFGR2_QPR_1 (((uint32_t)1 << 8))
#define ADC_CFGR2_QPR_F ((uint32_t)(0x0f << 8))
#define ADC_CFGR2_SCTNT_10H ((uint32_t)(0x10))
#define ADC_CFGR2_SCTNT_20H ((uint32_t)(0x20))

/*ADC sampling time register:ADC_SMPR*/
#define ADC_SMPR_SMP_6 ((uint32_t)(6))
#define ADC_SMPR_SMP_8 ((uint32_t)(8))
/*ADC watch dog register:ADC_WDG*/
#define ADC_ANALOG_WATCHDOG_EN (((uint32_t)1 << 7))
#define ADC_WATCHDOG_CHANNEL_MASK (((uint32_t)1 << 6))

/*ADC watch dog threshold register:ADC_TR*/
#define ADC_NOTE_FOR_HT_MASK (((uint32_t)1 << 28))
#define ADC_NOTE_FOR_LT_MASK (((uint32_t)1 << 12))

/*ADC channel selection register 1:ADC_CHSELR1*/
/*ADC channel selection register 2:ADC_CHSELR2*/
#define ADC_CHSELR_MASK ((uint8_t)(0x1F))
/*ADC FIFO access register:ADC_FIFO*/
/*ADC interrupt and status register 2:ADC_ISR2*/
#define ADC_FIFO_TIMEOUT_FLAG (((uint32_t)1 << 31))
#define ADC_DATA_BUFFER_TIMEOUT_FLAG (((uint32_t)1 << 15))
#define ADC_DATA_BUFFER_READY_FLAG (((uint32_t)1 << 12))

/*ADC data gather register:ADC_DGATR*/
#define ADC_DATA_BUFFER_TIMEOUT_INT_EN (((uint32_t)1 << 15))
#define ADC_DATA_BUFFER_TIMEOUT_EN (((uint32_t)1 << 14))
#define ADC_DATA_BUFFER_READY_INT_EN (((uint32_t)1 << 12))
#define ADC_DATA_GATHER_FUNCTION_EN (((uint32_t)1 << 0))

/*ADC data buffer register:ADC_DBUFR*/
/*ADC FIFO timeout register:ADC_FIFOTOR*/
#define ADC_FIFO_TIMEOUT_INT_EN (((uint32_t)1 << 15))
#define ADC_FIFO_TIMEOUT_EN (((uint32_t)1 << 14))

    /*ADC data for test 3:ADC_DFT3*/
    /*ADC data for test 2:ADC_DFT2*/
    /*ADC data for test 1:ADC_DFT1*/
    /*ADC data for test 0:ADC_DFT0*/
    /*ADC data for test 7:ADC_DFT7*/
    /*ADC data for test 6:ADC_DFT6*/
    /*ADC data for test 5:ADC_DFT5*/
    /*ADC data for test 4:ADC_DFT4*/
    /*ADC data for test 8:ADC_DFT8*/
    /*ADC channel selection register 3:ADC_CHSELR3*/

#endif /* end __ADC__ */

#define __CACHE__
#ifdef __CACHE__
/*** CACHE **********************************************/
/*** CCR ************/
#define CACHE_CCR_ENCACHE ((uint32_t)1 << 0) /*!< cache enable control bits, 1: enable cache*/
#define CACHE_CCR_INVW0 ((uint32_t)1 << 24)  /**< cache way0 all line Invalid*/
#define CACHE_CCR_PUSHW0 ((uint32_t)1 << 25) /**< push WAY 0 */
#define CACHE_CCR_INVW1 ((uint32_t)1 << 26)  /**< cache way1 all invalid lins push to way0 */
#define CACHE_CCR_PUSHW1 ((uint32_t)1 << 27) /**< push way1 line */
#define CACHE_CCR_GO ((uint32_t)1 << 31)     /**< Read cache command liveliness */

#define IPCCCR *(volatile uint32_t *)(ICACHE_BASE_ADDR + 0x0)
#define IPCCLCR *(volatile uint32_t *)(ICACHE_BASE_ADDR + 0x4)
#define IPCCSAR *(volatile uint32_t *)(ICACHE_BASE_ADDR + 0x8)
#define IPCCCVR *(volatile uint32_t *)(ICACHE_BASE_ADDR + 0xc)
#define IPCCSRR *(volatile uint32_t *)(ICACHE_BASE_ADDR + 0x10)

#define IPCCRGS *(volatile uint32_t *)(ICACHE_BASE_ADDR + 0x20)
#define IPCCRGS_H *(volatile uint32_t *)(ICACHE_BASE_ADDR + 0x24)

#define IR2HIGHADDR *(volatile uint32_t *)(ICACHE_BASE_ADDR + 0x80)

#define IPCRINVPAGEADDR *(volatile uint32_t *)(ICACHE_BASE_ADDR + 0x180)
#define IPCRINVPAGESIZE *(volatile uint32_t *)(ICACHE_BASE_ADDR + 0x184)

#define IPSCCR *(volatile uint32_t *)(ICACHE_BASE_ADDR + 0x800)
#define IPSCLCR *(volatile uint32_t *)(ICACHE_BASE_ADDR + 0x804)
#define IPSCSAR *(volatile uint32_t *)(ICACHE_BASE_ADDR + 0x808)
#define IPSCCVR *(volatile uint32_t *)(ICACHE_BASE_ADDR + 0x80c)
#define IPSCSRR *(volatile uint32_t *)(ICACHE_BASE_ADDR + 0x810)

#define IPSCRGS *(volatile uint32_t *)(ICACHE_BASE_ADDR + 0x820)

#define DPCCCR *(volatile uint32_t *)(DCACHE_BASE_ADDR + 0x0)
#define DPCCLCR *(volatile uint32_t *)(DCACHE_BASE_ADDR + 0x4)
#define DPCCSAR *(volatile uint32_t *)(DCACHE_BASE_ADDR + 0x8)
#define DPCCCVR *(volatile uint32_t *)(DCACHE_BASE_ADDR + 0xc)
#define DPCCSRR *(volatile uint32_t *)(DCACHE_BASE_ADDR + 0x10)

#define DPCCRGS *(volatile uint32_t *)(DCACHE_BASE_ADDR + 0x20)
#define DPCCRGS_H *(volatile uint32_t *)(DCACHE_BASE_ADDR + 0x24)

#define DR2HIGHADDR *(volatile uint32_t *)(DCACHE_BASE_ADDR + 0x80)

#define DPCRINVPAGEADDR *(volatile uint32_t *)(DCACHE_BASE_ADDR + 0x180)
#define DPCRINVPAGESIZE *(volatile uint32_t *)(DCACHE_BASE_ADDR + 0x184)

#define DPSCCR *(volatile uint32_t *)(DCACHE_BASE_ADDR + 0x800)
#define DPSCLCR *(volatile uint32_t *)(DCACHE_BASE_ADDR + 0x804)
#define DPSCSA *(volatile uint32_t *)(DCACHE_BASE_ADDR + 0x808)
#define DPSCCVR *(volatile uint32_t *)(DCACHE_BASE_ADDR + 0x80c)
#define DPSCSRR *(volatile uint32_t *)(DCACHE_BASE_ADDR + 0x810)

#define DPSCRGS *(volatile uint32_t *)(DCACHE_BASE_ADDR + 0x820)

#endif /* end __CACHE__ */

#define __CCM__
#ifdef __CCM__
///*** CCM **********************************************/
///*** FDCR 0x00************/
#define CCM_FDCR_LFDCR ((uint16_t)0xff << 0)
#define CCM_FDCR_HFDCR ((uint16_t)0xff << 8)

///*** CCR 0x02************/
#define CCM_CCR_BMT ((uint16_t)3 << 0)
#define CCM_CCR_BMD ((uint16_t)1 << 2)
#define CCM_CCR_BME ((uint16_t)1 << 3)
#define CCM_CCR_SHINT ((uint16_t)1 << 4)
#define CCM_CCR_PERIPH_BRIDGE_RAE ((uint16_t)1 << 5)
#define CCM_CCR_PERIPH_BRIDGE_PAE ((uint16_t)1 << 6)
#define CCM_CCR_MODE ((uint16_t)7 << 8)
#define CCM_CCR_CLKMODE_PDE ((uint16_t)1 << 11)
#define CCM_CCR_JTAGDIS ((uint16_t)1 << 12)
#define CCM_CCR_BTLDDIS ((uint16_t)1 << 13)
#define CCM_CCR_TESTDIS ((uint16_t)1 << 14)


///*** PCFG3 0x14************/
#define CCM_PCFG3_TDO_PUE ((uint32_t)1 << 10)

///*** RTCCFG12 0x18************/

///*** RTCCFG3 0x1c************/
#define CCM_RTCCFG3_RTC_TESTMODE_EN        ((uint32_t)1 << 17)
#define CCM_RTCCFG3_RSTOUT_CLKOUT_SR       ((uint32_t)1 << 10)
#define CCM_RTCCFG3_RSTOUT_CLKOUT_IS       ((uint32_t)1 << 11)
#define CCM_RTCCFG3_RSTOUT_PS              ((uint32_t)1 << 12)
#define CCM_RTCCFG3_CLKOUT_PS              ((uint32_t)1 << 13)


///*** PMCSR 0x20************/
#define CCM_PMCSR_OSC_2K_CLK_SRC       ((uint32_t)1 << 24)
#define CCM_PMCSR_OSC_128K_CLK_SRC     ((uint32_t)1 << 25)
// #define CCM_PMCSR_LVDT1P8V_SRC    ((uint32_t)1 << 26)
#define CCM_PMCSR_LVDT3P3V_SRC         ((uint32_t)1 << 27)

///*** SSICFGR 0x3C************/
#define CCM_SSICFGR_SSI4_XIP_EN        ((uint32_t)1 << 16)
#define CCM_SSICFGR_SSI4_DATA_ARRANGE  ((uint32_t)1 << 19)
#define CCM_SSICFGR_SSI4_XIP_SEL       ((uint32_t)1 << 20)
#define CCM_SSICFGR_SSI4_AUTO_WRAP_EN  ((uint32_t)1 << 24)

#endif /* end __CCM__ */

#define __CPM__
#ifdef __CPM__
/*** CPM **********************************************/

/*sleep config register:SLPCFGR 0x0000 ~ 0x0003*/
#if 1
#define CPM_SLPCFGR_LOW_POWER_MODE ((uint32_t)(0 << 30))
#define CPM_SLPCFGR_RETENTION_MODE (((uint32_t)1 << 30))
#define CPM_SLPCFGR_DEEP_SLEEP_MODE (((uint32_t)1 << 30))
#define CPM_SLPCFGR_HIBERNATION_MODE (((uint32_t)1 << 31))
#define CPM_SLPCFGR_EPORT2_MODULE_CLOCK_SLEEP_EN (((uint32_t)1 << 26)) /**< eport2 module clock enable when stop*/
#define CPM_SLPCFGR_EPORT1_MODULE_CLOCK_SLEEP_EN (((uint32_t)1 << 22)) /**< eport1 module clock enable when stop*/
#define CPM_SLPCFGR_EPORT0_MODULE_CLOCK_SLEEP_EN (((uint32_t)1 << 21)) /**< eport0 module clock enable when stop*/
#define CPM_SLPCFGR_PMU128K_SLEEP_EN (((uint32_t)1 << 19))             /**< PMU128K enable when stop*/
#define CPM_SLPCFGR_OTP_IPS_ENTER_LOWPOWER_EN (((uint32_t)1 << 4))        /**< OTP IP enter lowpower when stop*/
#define CPM_SLPCFGR_SSI_IDLE_WKPWAIT (((uint32_t)1 << 1))                 /**< SSI exit sleep before. ssi wait idle*/
#define CPM_SLPCFGR_SSI_IDLE_SLPWAIT (((uint32_t)1 << 0))                 /**< SSI enter sleep before. ssi wait idle*/

/*sleep control register:SLPCR 0x0004 ~ 0x0007*/
#define CPM_SLPCR_SLEEP_CONF_MODE (((uint32_t)1 << 29))

#else
#define CPM_SLPCFGR_SLEEP_MODE_POS (30U)          /*!< CPM SLPCFGR: SLEEP MODE Position */
#define CPM_SLPCFGR_SLEEP_MODE_MASK (0xC0000000U) /*!< CPM SLPCFGR: SLEEP MODE Mask */
#define CPM_SLPCFGR_LOW_POWER_MODE (0U << 31)
#define CPM_SLPCFGR_HIBERNATION_MODE (1U << 31)
#define CPM_SLPCFGR_LP_DIS_EN_POS (29U)                              /*!< CPM SLPCFGR: Lowpower Disable Position */
#define CPM_SLPCFGR_LP_DIS_EN_MASK (1U << CPM_SLPCFGR_LP_DIS_EN_POS) /*!< CPM SLPCFGR: Lowpower Disable Mask */
#define CPM_SLPCFGR_EXTFLASH_IPSLP_POS (26U)                         /*!< CPM SLPCFGR: Lowpower Disable Position */
#define CPM_SLPCFGR_EXTFLASH_IPSLP_MASK (0x1C000000U)                /*!< CPM SLPCFGR: Lowpower Disable Mask */
#define CPM_SLPCFGR_EXTFLASH_IPSLP_SSI4_MASK (1U << CPM_SLPCFGR_EXTFLASH_IPSLP_POS)
#define CPM_SLPCFGR_EXTFLASH_IPSLP_SSI5_MASK (1U << 27U)
#define CPM_SLPCFGR_EXTFLASH_IPSLP_SSI6_MASK (1U << 28U)
#define CPM_SLPCFGR_MCC_SLPEN_POS (23U)                                                /*!< CPM SLPCFGR: MCC Sleep Enable Position */
#define CPM_SLPCFGR_MCC_SLPEN_MASK (1U << CPM_SLPCFGR_MCC_SLPEN_POS)                   /*!< CPM SLPCFGR: MCC Sleep Enable Mask */
#define CPM_SLPCFGR_HP_READY_WKPWAIT_POS (22U)                                         /*!< CPM SLPCFGR: Wait HPLDO READY Position */
#define CPM_SLPCFGR_HP_READY_WKPWAIT_MASK (1U << CPM_SLPCFGR_HP_READY_WKPWAIT_POS)     /*!< CPM SLPCFGR: Wait HPLDO READY Mask */
#define CPM_SLPCFGR_WAKEUP_NM_SLPWAIT_POS (21U)                                        /*!< CPM SLPCFGR: Wait WAKEUP NM Position */
#define CPM_SLPCFGR_WAKEUP_NM_SLPWAIT_MASK (1U << CPM_SLPCFGR_WAKEUP_NM_SLPWAIT_POS)   /*!< CPM SLPCFGR: Wait WAKEUP NM Mask */
#define CPM_SLPCFGR_OSCEXT_SLEEP_EN_POS (20U)                                          /*!< CPM SLPCFGR: OSCEXT SLEEP Enable Position */
#define CPM_SLPCFGR_OSCEXT_SLEEP_EN (1U << CPM_SLPCFGR_OSCEXT_SLEEP_EN_POS)            /*!< CPM SLPCFGR: OSCEXT SLEEP Enable Mask */
#define CPM_SLPCFGR_PMU128K_SLEEP_EN_POS (19U)                                         /*!< CPM SLPCFGR: PMU128K SLEEP Enable Position */
#define CPM_SLPCFGR_PMU128K_SLEEP_EN_MASK (1U << CPM_SLPCFGR_PMU128K_SLEEP_EN_POS)     /*!< CPM SLPCFGR: PMU128K SLEEP Enable Mask */
#define CPM_SLPCFGR_RTC32K__SLEEP_EN_POS (16U)                                         /*!< CPM SLPCFGR: RTC32K SLEEP Enable Position */
#define CPM_SLPCFGR_RTC32K_SLEEP_EN_MASK (1U << CPM_SLPCFGR_RTC32K__SLEEP_EN_POS)      /*!< CPM SLPCFGR: RTC32K SLEEP Enable Mask */
#define CPM_SLPCFGR_CARD0_LDO_POWEROFF_POS (11)                                        /*!< CPM SLPCFGR: CARD0 LDO POWEROFF Position */
#define CPM_SLPCFGR_CARD0_LDO_POWEROFF_MASK (1U << CPM_SLPCFGR_CARD0_LDO_POWEROFF_POS) /*!< CPM SLPCFGR: CARD0 LDO POWEROFF Mask */
#define CPM_SLPCFGR_CARD0_LDO_POWER_POS (8)                                            /*!< CPM SLPCFGR: CARD0 LDO POWER Position */
#define CPM_SLPCFGR_CARD0_LDO_POWER_MASK (0x00000300U)                                 /*!< CPM SLPCFGR: CARD0 LDO POWER Mask */
#define CPM_SLPCFGR_CARD0_LDO_VOTAGE_OUT_1V8 (0U << CPM_SLPCFGR_CARD0_LDO_POWER_POS)
#define CPM_SLPCFGR_CARD0_LDO_VOTAGE_OUT_3V0 (1U << CPM_SLPCFGR_CARD0_LDO_POWER_POS)
#define CPM_SLPCFGR_CARD0_LDO_VOTAGE_OUT_3V3 (3U << CPM_SLPCFGR_CARD0_LDO_POWER_POS)
#define CPM_SLPCFGR_OTP_IPSLP_POS (4U)                                             /*!< CPM SLPCFGR: OPT IP SLEEP Position */
#define CPM_SLPCFGR_OTP_IPSLP_MASK (1U << CPM_SLPCFGR_OTP_IPSLP_POS)               /*!< CPM SLPCFGR: OPT IP SLEEP Mask */
#define CPM_SLPCFGR_SSI_IDLE_WKPWAIT_POS (1U)                                      /*!< CPM SLPCFGR: WAKEUP WAIT SSI IDLE Position */
#define CPM_SLPCFGR_SSI_IDLE_WKPWAIT_MASK (1U << CPM_SLPCFGR_SSI_IDLE_WKPWAIT_POS) /*!< CPM SLPCFGR: WAKEUP WAIT SSI IDLE Mask */
#define CPM_SLPCFGR_SSI_IDLE_SLPWAIT_POS (0U)                                      /*!< CPM SLPCFGR: SLEEP WAIT SSI IDLE Position */
#define CPM_SLPCFGR_SSI_IDLE_SLPWAIT_MASK (1U << CPM_SLPCFGR_SSI_IDLE_SLPWAIT_POS) /*!< CPM SLPCFGR: SLEEP WAIT SSI IDLE Mask */

/*sleep control register:SLPCR 0x0004 ~ 0x0007*/
#define CPM_SLPCR_SLP_CFG_KEY_POS (30U)                                            /*!< CPM SLPCR: SLEEP CONFIG KEY Position */
#define CPM_SLPCR_SLP_CFG_KEY_MASK (0xC0000000U)                                   /*!< CPM SLPCR: SLEEP CONFIG KEY Mask */
#define CPM_SLPCR_SLP_CFG_MODE_POS (29U)                                           /*!< CPM SLPCR: SLEEP CONFIG MODE Position */
#define CPM_SLPCR_SLP_CFG_MODE_MASK (1U << CPM_SLPCR_SLP_CFG_MODE_POS)             /*!< CPM SLPCR: SLEEP CONFIG MODE Mask */
#endif

/*system clock divider register:SCDIVR 0x0008 ~ 0x000B*/
#define CPM_SCDIVR_CLKOUT_DIV_MASK ((uint32_t)(0xFF00FFFF)) /**< */
#define CPM_SCDIVR_CLKOUT_DIV_SHIFT_MASK (((uint32_t)16))   /**<  */
#define CPM_SCDIVR_TRACE_DIV_MASK ((uint32_t)(0xFFFF00FF))  /**< */
#define CPM_SCDIVR_TRACE_DIV_SHIFT_MASK ((uint32_t)(8))     /**<  */
#define CPM_SCDIVR_SYS_DIV_MASK ((uint32_t)(0xFFFFFF00))    /**< */
#define CPM_SCDIVR_SYS_DIV_SHIFT_MASK ((uint32_t)(0))       /**< */

/*periphal clock divider register 1:PCDIVR1 0x000C ~ 0x000F*/
#define CPM_PCDIVR_ARITH_DIV_MASK ((uint32_t)(0xFFFF0FFF)) /**< */
#define CPM_PCDIVR_ARITH_DIV_SHIFT_MASK (((uint32_t)12))   /**< */
#define CPM_PCDIVR_AHB3_DIV_MASK ((uint32_t)(0xFFFFF0FF))  /**< */
#define CPM_PCDIVR_AHB3_DIV_SHIFT_MASK ((uint32_t)(8))     /**< */
#define CPM_PCDIVR_IPS_DIV_MASK ((uint32_t)(0xFFFFFFF0))   /**< */
#define CPM_PCDIVR_IPS_DIV_SHIFT_MASK ((uint32_t)(0))      /**< */

/*periphal clock divider register 2:PCDIVR2 0x0010 ~ 0x0013*/
#define CPM_PCDIVR_TC_DIV_MASK ((uint32_t)(0x0FFFFFFF))      /**< */
#define CPM_PCDIVR_TC_DIV_SHIFT_MASK ((uint32_t)(28))        /**<  */
#define CPM_PCDIVR_ADC_DIV_MASK ((uint32_t)(0xFFFF0FFF))     /**< */
#define CPM_PCDIVR_ADC_DIV_SHIFT_MASK (((uint32_t)12))       /**< */

/*periphal clock divider register 3:PCDIVR3 0x0010 ~ 0x0013*/
/*clock divider update register??CDIVUPDR 0x0018 ~ 0x001B*/
#define CPM_CDIVUPDR_SYS_DIV_UPDATE (((uint32_t)1 << 1))        /**< sys clk update*/
#define CPM_CDIVUPDR_PERIPHERAL_DIV_UPDATE (((uint32_t)1 << 0)) /**< peripheral clk update*/

/*clock divider enable register??CDIVENR 0x001C ~ 0x001F*/
#define CPM_CDIVENR_CLKOUT_CLK_DIV_EN (((uint32_t)1 << 15))
#define CPM_CDIVENR_TRACE_CLK_DIV_EN (((uint32_t)1 << 14))
#define CPM_CDIVENR_TC_CLK_DIV_EN (((uint32_t)1 << 13))
#define CPM_CDIVENR_ADC_CLK_DIV_EN (((uint32_t)1 << 10))
#define CPM_CDIVENR_ARITH_CLK_DIV_EN (((uint32_t)1 << 3))
#define CPM_CDIVENR_AHB3_CLK_DIV_EN (((uint32_t)1 << 2))
#define CPM_CDIVENR_IPS_CLK_DIV_EN (((uint32_t)1 << 0))

/*oscillator control and status register??OCSR 0x0020 ~ 0x0023*/
#define CPM_OCSR_TRNG_OSCEN ((uint32_t)(0xF << 24))      /**< */
#define CPM_OCSR_PMU2K_STABLE (((uint32_t)1 << 14))      /**< */
#define CPM_OCSR_OSCEXT_STABLE (((uint32_t)1 << 12))     /**< */
#define CPM_OCSR_OSC400M_STABLE (((uint32_t)1 << 11))    /**< */
#define CPM_OCSR_PMU128K_STABLE (((uint32_t)1 << 9))     /**< */
#define CPM_OCSR_OSC8M_STABLE (((uint32_t)1 << 8))       /**< */
#define CPM_OCSR_PMU2K_CLK_EN (((uint32_t)1 << 6))
#define CPM_OCSR_OSCEXT_CLK_EN (((uint32_t)1 << 4))
#define CPM_OCSR_OSC400M_CLK_EN (((uint32_t)1 << 3))
#define CPM_OCSR_PMU128K_CLK_EN (((uint32_t)1 << 1))
#define CPM_OCSR_OSC8M_CLK_EN (((uint32_t)1 << 0))

/*clock switch config register: CSWCFGR 0x0024 ~ 0x0027*/
#define CPM_CSWCFGR_OSC8M_SELECT (((uint32_t)1 << 8))            /**< */
#define CPM_CSWCFGR_OSC400M_SELECT (((uint32_t)1 << 9))          /**< */
#define CPM_CSWCFGR_OSCEXT_SELECT (((uint32_t)1 << 11))          /**< */
#define CPM_CSWCFGR_SOC_CLK_SOURCE_MASK ((uint32_t)(0xFFFFFFFC)) /**< */
#define CPM_CSWCFGR_CLKOUT_SOURCE_SYS ((uint32_t)(0 << 24))      /**< */
#define CPM_CSWCFGR_CLKOUT_SOURCE_ARITH (((uint32_t)1 << 24))    /**< */
#define CPM_CSWCFGR_CLKOUT_SOURCE_PLLNFC ((uint32_t)(2 << 24))   /**< */
#define CPM_CSWCFGR_CLKOUT_SOURCE_OSCL ((uint32_t)(3 << 24))     /**< */

/*core tick timer register:CTICKR 0x0028 ~ 0x002B*/
#define CPM_CTICKR_REFERENCE_CLK_SELECT_MASK (((uint32_t)1 << 25)) /**< */
#define CPM_CTICKR_SKEW_EN (((uint32_t)1 << 24))                   /**< */

/*chip config register:CHIPCFGR:CHIPCFGR 0x002C ~ 0x002F*/
#define CPM_CHIPCFGR_RIM_ARST_MASK (((uint32_t)1 << 10))
#define CPM_CHIPCFGR_RIM_RST_MASK (((uint32_t)1 << 9))
#define CPM_CHIPCFGR_RIM_SOFTRST_MASK (((uint32_t)1 << 8))

/*power control register:PWRCR 0x0030 ~ 0x0033*/
#define CPM_PWRCR_VCC_IO_LATCH_CLR_MASK ((uint32_t)1 << 31)
#define CPM_PWRCR_VCC_IO_LATCH_SET_MASK ((uint32_t)1 << 30)
#define CPM_PWRCR_VCC_3V3_LV_DETECT_RESET_EN (((uint32_t)1 << 29))
#define CPM_PWRCR_VCARD0_INTERFACE_ISOLATION_EN (((uint32_t)1 << 25))
#define CPM_PWRCR_VCC_3V3_LVD_POWERDOWN_MASK (((uint32_t)1 << 23))
#define CPM_PWRCR_CARD0_LV_DETECT_RESET_EN (((uint32_t)1 << 9))
#define CPM_PWRCR_VCC_3V3_LV_DETECT_INT_EN (((uint32_t)1 << 15))
#define CPM_PWRCR_CARD0_LV_DETECT_INT_EN (((uint32_t)1 << 13))
#define CPM_PWRCR_CARD0_IE_EN_FAIL (((uint32_t)1 << 11))
#define CPM_PWRCR_CARD0_RE_LVD (((uint32_t)1 << 9))
#define CPM_PWRCR_VCC_OE_LVDT33 (((uint32_t)1 << 7))
#define CPM_PWRCR_CARD0_OE_LVD (((uint32_t)1 << 5))
#define CPM_PWRCR_VCC_3V3_LV_DETECT_EN (((uint32_t)1 << 3))
#define CPM_PWRCR_CARD0_LV_DETECT_EN (((uint32_t)1 << 1))

/*sleep counter register:SLPCNTR 0x0034~ 0x0037*/

/*wake up counter register:WKPCNTR 0x0038~ 0x003B*/

/*multiple clock gate control register:MULTICGTCR ??0x003C ~ 0x003F*/
/*system clock gate control register:SYSCGTCR 0x0040 ~ 0x0043*/
/*ahb3 clock gate control register:AHB3CGTCR 0x0044 ~ 0x0047*/
/*arith clock gate control register:ARITHCGTCR 0x0048 ~ 0x004B*/
/*ips clock gate control register:IPSCGTCR 0x004C ~ 0x004F*/

/*vcc general trim register:VCCGTRIMR 0x0050 ~ 0x0053*/
#define CPM_VCCGTRIMR_DISCHARGE_EN (((uint32_t)1 << 30)) /**< when this bit is set,discharge vd33 when chip switch to poff2 mode*/
#define CPM_VCCGTRIMR_2KHZ_CLK_GATE_EN (((uint32_t)1 << 23))
#define CPM_VCCGTRIMR_CORE_VOLTAGE_MASK (((uint32_t)1 << 15)) /**< when this bit is set, the core voltage is 0.9V*/
#define CPM_VCCGTRIMR_VCC_LATCH_AUTO_SET_MASK (((uint32_t)1 << 13))
#define CPM_VCCGTRIMR_VCC_LATCH_AUTO_CLR_MASK (((uint32_t)1 << 12))
#define CPM_VCCGTRIMR_VCC_LATCH_AUTO_PORCLR (((uint32_t)1 << 11))
#define CPM_VCCGTRIMR_TEST_BIAS_CURRENT_EN (((uint32_t)1 << 7)) /**< test the bias current enable signal*/

/*vcc lv detect trim register:VCCLTRIMR 0x0054 ~ 0x0057*/
#define CPM_VCCLTRIMR_OTP_LVDT_MASK (((uint32_t)1 << 25))
#define CPM_VCCLTRIMR_COARSE_LVD_MODULE_EN (((uint32_t)1 << 24))

/*vcc vref trim register:VCCVTRIMR 0x0058 ~ 0x005B*/
#define CPM_VCCVTRIMR_SLEEP_CONF_REG_PROTECT_EN (((uint32_t)1 << 31))
#define CPM_VCCVTRIMR_POFF2_WAKEUP_SOURCE_USBDET           (((uint32_t)1<<16))
#define CPM_VCCVTRIMR_VREF_STABLE_MASK (((uint32_t)1 << 11))
#define CPM_VCCVTRIMR_VREF_TRIM_EN (((uint32_t)1 << 10))
#define CPM_VCCVTRIMR_VREF_TRIM_VALUE_LOAD_BIT (((uint32_t)1 << 9))
#define CPM_VCCVTRIMR_STORE_VREF_VOLTAGE_VALUE_EN (((uint32_t)1 << 8))

/*vcc core test mode register:VCCCTMR 0x005C ~ 0x005F*/
#define CPM_VCCCTMR_OVERWRITE_CSWCFGR_TRIM_EN (((uint32_t)1 << 29))
#define CPM_VCCCTMR_OVERWRITE_RTCTRIMR_TRIM_EN (((uint32_t)1 << 28))
#define CPM_VCCCTMR_OVERWRITE_RTCSTIMER_TRIM_EN (((uint32_t)1 << 26))
#define CPM_VCCCTMR_OVERWRITE_CARDTRIMR_TRIM_EN (((uint32_t)1 << 24))
#define CPM_VCCCTMR_OVERWRITE_VCCGTRIMR_TRIM_EN (((uint32_t)1 << 23))
#define CPM_VCCCTMR_OVERWRITE_VCCLTRIMR_TRIM_EN (((uint32_t)1 << 22))
#define CPM_VCCCTMR_OVERWRITE_VCCVTRIMR_TRIM_EN (((uint32_t)1 << 21))
#define CPM_VCCCTMR_OVERWRITE_O8MTRIMR_TRIM_EN (((uint32_t)1 << 20))
#define CPM_VCCCTMR_OVERWRITE_O320MTRIMR_TRIM_EN (((uint32_t)1 << 19))
#define CPM_VCCCTMR_OVERWRITE_OSCLSTIMER_TRIM_EN (((uint32_t)1 << 18))
#define CPM_VCCCTMR_OVERWRITE_OSCHSTIMER_TRIM_EN (((uint32_t)1 << 17))
#define CPM_VCCCTMR_OVERWRITE_OSCESTIMER_TRIM_EN (((uint32_t)1 << 16))
#define CPM_VCCCTMR_OVERWRITE_ARITHCGTCR_TRIM_EN (((uint32_t)1 << 13))
#define CPM_VCCCTMR_OVERWRITE_SCDIVR_TRIM_EN (((uint32_t)1 << 11))
#define CPM_VCCCTMR_OVERWRITE_PCDIVR_TRIM_EN (((uint32_t)1 << 10))
#define CPM_VCCCTMR_OVERWRITE_OCSR_TRIM_EN (((uint32_t)1 << 9))
#define CPM_VCCCTMR_CPU_CORE_TEST_MODE_EN (((uint32_t)1 << 7))
#define CPM_VCCCTMR_SOFT_POR (((uint32_t)1 << 3))
#define CPM_VCCCTMR_OFF_MODE2 (((uint32_t)1 << 2))
#define CPM_VCCCTMR_EN_LP (((uint32_t)1 << 0))

/*osc8mhz trim register:O8MTRIMR 0x0060 ~ 0x0063*/


/*card ldo trim trgister:CARDTRIMR 0x006C ~ 0x006F*/
#define CPM_CARDTRIMR_WAKEUP_FILTER_EN (((uint32_t)1 << 30))
#define CPM_CARDTRIMR_WAKEUP_FILTER_BYPASS_EN (((uint32_t)1 << 29))
#define CPM_CARDTRIMR_WAKEUP_FILTER_CLK_GATE_EN (((uint32_t)1 << 28))
#define CPM_CARDTRIMR_WAKEUP_VDD33_PSWEN (((uint32_t)1 << 24))
#define CPM_CARDTRIMR_WAKEUP_ANALOG_FILTER_BYPASS_EN (((uint32_t)1 << 15))
#define CPM_CARDTRIMR_CARD0_REDUCE (((uint32_t)1 << 13))

/*oscl stable time register:OSCLSTIMER 0x0070 ~ 0x0073*/
/*osch stable time register:OSCHSTIMER 0x0074 ~ 0x0077*/
/*osce stable time register:OSCESTIMER 0x0078 ~ 0x007B*/

/*power status register:PWRSR 0x007C ~ 0x007F*/
#define CPM_PWRSR_VCARD_ISOLATION_FLAG (((uint32_t)1 << 26))
#define CPM_PWRSR_VCC3V3_LVD_FLAG (((uint32_t)1 << 23))
#define CPM_PWRSR_CARD0_LVD_FLAG (((uint32_t)1 << 21))
#define CPM_PWRSR_VCC3V3_LVD_REAL_TIME_FLAG (((uint32_t)1 << 19))
#define CPM_PWRSR_CARD0_LVD_REAL_TIME_FLAG (((uint32_t)1 << 17))
#define CPM_PWRSR_CARD0_LVD_FAIL_FLAG (((uint32_t)1 << 15))
#define CPM_PWRSR_VCC_HIGH_POWER_READY_FLAG (((uint32_t)1 << 3))
#define CPM_PWRSR_CARD0_READY_FLAG (((uint32_t)1 << 2))

/*eport sleep control register:EPORTSLPCFGR 0x0080 ~ 0x0083*/
/*eport clock gate control register:EPORTCGTR 0x0084 ~ 0x0087*/
/*eport reset control register:EPORTRSTCR 0x0088 ~ 0x008B*/

/*rtc trim register:RTCTRIMR 0x008C~ 0x008F*/

/*pad wakeup interrupt control register:PADWKINTCR 0x0090~ 0x0093*/

#define CPM_PADWKINTCR_RIM_ARST_RT (((uint32_t)1 << 31))
#define CPM_PADWKINTCR_DBG_PWRUP_RT (((uint32_t)1 << 30))
#define CPM_PADWKINTCR_TCRST_RT (((uint32_t)1 << 28))
#define CPM_PADWKINTCR_WAKE_WAKEUP_SRC_STATUS (((uint32_t)1 << 25))
#define CPM_PADWKINTCR_RIM_ARST_EN (((uint32_t)1 << 23))
#define CPM_PADWKINTCR_DBG_PWRUP_EN (((uint32_t)1 << 22))
#define CPM_PADWKINTCR_TCRST_EN                            (((uint32_t)1<<20))
#define CPM_PADWKINTCR_WAKE_WAKEUP_SRC_EN (((uint32_t)1 << 17))
#define CPM_PADWKINTCR_RIM_ARST_INTM (((uint32_t)1 << 15))
#define CPM_PADWKINTCR_DBG_PWRUP_INTM (((uint32_t)1 << 14))
#define CPM_PADWKINTCR_TCRST_INTM (((uint32_t)1 << 12))
#define CPM_PADWKINTCR_WAKE_WAKEUP_SRC_INT_EN (((uint32_t)1 << 9))
#define CPM_PADWKINTCR_RIM_ARST_STAT (((uint32_t)1 << 7))
#define CPM_PADWKINTCR_DBG_PWRUP_STAT (((uint32_t)1 << 6))
#define CPM_PADWKINTCR_TCRST_STAT (((uint32_t)1 << 4))
#define CPM_PADWKINTCR_WAKE_WAKEUP_SRC_INT_FLAG (((uint32_t)1 << 1))
/*wakeup filter counter register:FILTCNTR 0x0094~ 0x0097*/
/*card power on counter register:CARDPOCR 0x0098~ 0x009B*/
/*rtc 32k stable time register:RTCSTIMER 0x009C~ 0x009F*/
/*mem power down sleep control register:MPDSLPCR 0x00A0 ~ 0x00A3*/
/*multiple reset control register:MULTIRSTCR 0x00AC ~ 0x00AF*/
/*system reset control register:SYSRSTCR 0x00B0~ 0x00B3*/
/*ahb3 reset control register:AHB3RSTCR 0x00B4~ 0x00B7*/
/*arith reset control register:ARITHRSTTCR 0x00B8 ~ 0x00BB*/
/*ips reset control register:IPRSTCR 0x00BC ~ 0x00BF*/

/*sleep config register 2:SLPCFGR2 0x00C0 ~ 0x00C3*/
#define CPM_SLPCFGR2_RIM_ARST_INTM_SGL (((uint32_t)1 << 23))
#define CPM_SLPCFGR2_DBG_PWRUP_INTM_SGL (((uint32_t)1 << 22))
#define CPM_SLPCFGR2_ISORST_INTM_SGL (((uint32_t)1 << 21))
#define CPM_SLPCFGR2_TCRST_INTM_SGL (((uint32_t)1 << 20))
#define CPM_SLPCFGR2_WAKE_WAKEUP_SRC_SGL_INT_EN (((uint32_t)1 << 17))
#define CPM_SLPCFGR2_USB_DET_WAKEUP_SRC_SGL_INT_EN (((uint32_t)1 << 16))
#define CPM_SLPCFGR2_TRNG_SLPEN (((uint32_t)1 << 15))
#define CPM_SLPCFGR2_OTP_IDLE_WKPWAIT (((uint32_t)1 << 14))
#define CPM_SLPCFGR2_OTP_IDLE_SLPWAIT (((uint32_t)1 << 13))
#define CPM_SLPCFGR2_CACHE_IDLE_SLPWAIT (((uint32_t)1 << 12))
#define CPM_SLPCFGR2_CORE_F_CLK_SLEEP_EN (((uint32_t)1 << 11))
#define CPM_SLPCFGR2_CLKOUT_CLK_SLEEP_EN (((uint32_t)1 << 10))
#define CPM_SLPCFGR2_CPM_IPS_CLK_SLEEP_EN (((uint32_t)1 << 9))
#define CPM_SLPCFGR2_TC_CLK_SLEEP_EN (((uint32_t)1 << 8))
#define CPM_SLPCFGR2_CAN_IDLE_SLPWAIT (((uint32_t)1 << 6))

/*power down counter register:PDNCNTR 0x00D0 ~ 0x00D3*/

/*power down counter register:PONCNTR 0x00D4 ~ 0x00D7*/

/*periphal clock divider register 4:PCDIVR4 0x00D8 ~ 0x00DB*/

/*pll nfc config register 4:PLLNFCCFGR 0x00E0 ~ 0x00E3*/
#define CPM_PLLNFCCFGR_TEST_PORT_EN (((uint32_t)1 << 26))
#define CPM_PLLNFCCFGR_TEST_EN (((uint32_t)1 << 25))
#define CPM_PLLNFCCFGR_EN_XTAL (((uint32_t)1 << 24))

    /*pll nfc time stable register 4:PLLNFCCFGR 0x00E4 ~ 0x00E7*/

#endif /* end __CPM__ */

#define __CRC__
#ifdef __CRC__
/*** CRC **********************************************/
#define CRC_MODE_CRC_32 				((uint32_t)4)                 
#define CRC_MODE_CRC_16 				((uint32_t)2)                  
#define CRC_MODE_CRC_8  				((uint32_t)1)                 
#define CRC_MODE_MASK 					((uint32_t)0x1FFFFFFF)         
#define CRC_MODE_UPDATA 				(((uint32_t)1 << 28))          
#define CRC_MODE_SOURCE_SEL_DMAC_WRITE 	(((uint32_t)1 << 27)) 		 
#define CRC_MODE_BIG_ENDING 			(((uint32_t)1 << 26))          
#define CRC_DECODE 						(((uint32_t)1 << 18))         
#define CRC_SEND_CRC_CODE_EN 			(((uint32_t)1 << 17))        
#define CRC_WRITE_CRC_CODE_EN 			(((uint32_t)1 << 16))         

#define CRC_OK 							(((uint32_t)1 << 0))          

#endif /* end __CRC__ */

#define __DMAC__
#ifdef __DMAC__
/*** DMAC **********************************************/
/*DMAC_CTRLn*/
#define DMAC_INT_MIN (((uint32_t)1 << 31))
#define DMAC_LLP_SRC_EN (((uint32_t)1 << 28))             /**<  */
#define DMAC_LLP_DST_EN (((uint32_t)1 << 27))             /**<  */
#define DMAC_TT_FC_MASK ((uint32_t)(0x00700000))          /**< */
#define DMAC_TT_FC_SHIFT_MASK ((uint32_t)(20))            /**<   */
#define DMAC_TT_FC_BITS_MASK ((uint32_t)(0xFF8FFFFF))     /**< */
#define DMAC_SRC_MSIZE_MASK ((uint32_t)(0x0001C000))      /**< */
#define DMAC_SRC_MSIZE_SHIFT_MASK (((uint32_t)14))        /**< */
#define DMAC_SRC_MSIZE_BITS_MASK ((uint32_t)(0xFFFE3FFF)) /**< */

#define DMAC_DEST_MSIZE_MASK ((uint32_t)(0x00003800))      /**< */
#define DMAC_DEST_MSIZE_SHIFT_MASK (((uint32_t)11))        /**<   */
#define DMAC_DEST_MSIZE_BITS_MASK ((uint32_t)(0xFFFC7FFF)) /**< */

#define DMAC_SINC_INC (((uint32_t)1 << 0))
#define DMAC_SINC_DEC                                      (((uint32_t)1<<9)
#define DMAC_SINC_NO_CHANGE (((uint32_t)1 << 10))
#define DMAC_SINC_INC_MASK ((uint32_t)(0x00000600))      /**< */
#define DMAC_SINC_INC_SHIFT_MASK ((uint32_t)(9))         /**<   */
#define DMAC_SINC_INC_BITS_MASK ((uint32_t)(0xFFFFF9FF)) /**< */

#define DMAC_DINC_INC (((uint32_t)1 << 0))
#define DMAC_DINC_DEC                                      (((uint32_t)1<<7)
#define DMAC_DINC_NO_CHANGE (((uint32_t)1 << 8))
#define DMAC_DINC_INC_MASK ((uint32_t)(0x00000180))      /**< */
#define DMAC_DINC_INC_SHIFT_MASK ((uint32_t)(7))         /**<  */
#define DMAC_DINC_INC_BITS_MASK ((uint32_t)(0xFFFFFE7F)) /**< */

#define DMAC_SRC_TR_WIDTH_MASK ((uint32_t)(0x00000070))      /**< */
#define DMAC_SRC_TR_WIDTH_SHIFT_MASK ((uint32_t)(4))         /**<  */
#define DMAC_SRC_TR_WIDTH_BITS_MASK ((uint32_t)(0xFFFFFF1F)) /**< */
#define DMAC_DST_TR_WIDTH_MASK ((uint32_t)(0x00000007))      /**< */
#define DMAC_DST_TR_WIDTH_SHIFT_MASK (((uint32_t)1))         /**<  */
#define DMAC_DST_TR_WIDTH_BITS_MASK ((uint32_t)(0xFFFFFFF1)) /**< */
#define DMAC_INT_EN (((uint32_t)1 << 0))
/*DMA_CFGn*/
#define DMAC_MAX_ABRS_MASK ((uint32_t)(0x3FF00000))
#define DMAC_MAX_ABRS_SHIFT_MASK ((uint32_t)(20)) /* */
#define DMAC_MAX_ABRS_BITS_MASK ((uint32_t)(0xC00FFFFF))
#define DMAC_HS_SEL_SRC (((uint32_t)1 << 11))
#define DMAC_HS_SEL_DST (((uint32_t)1 << 10))
#define DMAC_FIFO_EMPTY (((uint32_t)1 << 9))
#define DMAC_CH_SUSP (((uint32_t)1 << 8))

#define DMAC_CH_PRIOR_MASK ((uint32_t)(0x000000E0))
#define DMAC_CH_PRIOR_SHIFT_MASK ((uint32_t)(5)) /* */
#define DMAC_CH_PRIOR_BITS_MASK ((uint32_t)(0xFFFFFF1F))

/*DMA_CFG_HIGHn*/
#define DMAC_DST_PER_MASK ((uint32_t)(0x00007800))
#define DMAC_DST_PER_SHIFT_MASK (((uint32_t)11)) /* */
#define DMAC_DST_PER_BITS_MASK ((uint32_t)(0xFFFF87FF))

#define DMAC_SRC_PER_MASK ((uint32_t)(0x00000780))
#define DMAC_SRC_PER_SHIFT_MASK ((uint32_t)(7)) /* */
#define DMAC_SRC_PER_BITS_MASK ((uint32_t)(0xFFFFF87F))

#define DMAC_FC_MODE (((uint32_t)1 << 0))

/**/
#define DMAC_CH_WE_EN_SHIFT_MASK ((uint32_t)(8)) /* */
#define DMAC_CH_EN_MASK ((uint32_t)(0x0000000F))
#define DMAC_EN ((uint8_t)(1 << 0))
    /**/

#endif /* end __DMAC__ */

#define __EDMAC__
#ifdef __EDMAC__
/*** EDMAC **********************************************/
/*EDMACCR*/
#define EDMAC_PIPELINE_EN (((uint32_t)1 << 31))  /**< */
#define EDMAC_SPI_HW (((uint32_t)1 << 30))       /**< */
#define EDMAC_PRIOR_CHG_EN (((uint32_t)1 << 29)) /**< */
#define EDMAC_PRIOR (((uint32_t)1 << 28))        /**< */
#define EDMAC_SPI_WROPT_EN (((uint32_t)1 << 27)) /**< */
#define EDMAC_INFINITY_EN (((uint32_t)1 << 26))  /**< */
#define EDMAC_SPI_FIFO_PRE_LOAD_3 (((uint32_t)1 << 25))

#define EDMAC_MAJ_DONE_IT_EN (((uint32_t)1 << 24))                      /**<                                            */
#define EDMAC_MAJ_DONE_IT_DIS ((uint32_t) ~(1 << EDMAC_MAJ_DONE_IT_EN)) /**<                                            */

#define EDMAC_MAJ_CRC_SEL_MAJOR (((uint32_t)1 << 23))                        /**< operation takes place when major loop ends */
#define EDMAC_MAJ_CRC_SEL_MINOR ((uint32_t) ~(1 << EDMAC_MAJ_CRC_SEL_MAJOR)) /**< operation takes place when minor loop ends */

#define EDMAC_CRC_CHANNEL_EN (((uint32_t)1 << 22))                                  /**<                                            */
#define EDMAC_CRC_CHANNEL_DIS ((uint32_t) ~(1 << EDMAC_CRC_CHANNEL_EN))             /**<                                            */
#define EDMAC_SEND_CRC_CHANNEL_EN (((uint32_t)1 << 21))                             /**<                                            */
#define EDMAC_SEND_CRC_CHANNEL_DIS ((uint32_t) ~(1 << EDMAC_SEND_CRC_CHANNEL_EN))   /**<                                            */
#define EDMAC_WRITE_CRC_CHANNEL_EN (((uint32_t)1 << 20))                            /**<                                            */
#define EDMAC_WRITE_CRC_CHANNEL_DIS ((uint32_t) ~(1 << EDMAC_WRITE_CRC_CHANNEL_EN)) /**<                                            */
#define EDMAC_LINK_SRC_SEL_MASK ((uint32_t)(0xFFF9FFFF))                            /**<                                            */
#define EDMAC_LINK_SRC_SEL_SHIFT_MASK ((uint8_t)(1 << 17))
/**<                                                         */
//#define EDMAC_LINK_SRC_EDMAC0_CH0_DONE ((uint8_t)(0x00 << EDMAC_LINK_SRC_SEL_MASK)) /**<                                            */
//#define EDMAC_LINK_SRC_EDMAC0_CH1_DONE ((uint8_t)( (uint32_t)1 << EDMAC_LINK_SRC_SEL_MASK)) /**<                                            */
#define EDMAC_LINK_SRC_EDMAC1_CH0_DONE ((uint8_t)(0x02 << EDMAC_LINK_SRC_SEL_MASK)) /**<                                            */
#define EDMAC_LINK_SRC_EDMAC1_CH1_DONE ((uint8_t)(0x03 << EDMAC_LINK_SRC_SEL_MASK)) /**<                                            */

#define EDMAC_LINK_EN (((uint32_t)1 << 16))                                                  /**<                                            */
#define EDMAC_LINK_DIS ((uint32_t)(EDMAC_LINK_EN))                                           /**<                                            */
#define EDMAC_COMPARE_EN (((uint32_t)1 << 15))                                               /**<                           */
#define EDMAC_COMPARE_DIS ((uint32_t)(EDMAC_COMPARE_EN))                                     /**<                           */
#define EDMAC_COMPARE_SKIP_EN (((uint32_t)1 << 14))                                          /**<                        */
#define EDMAC_COMPARE_SKIP_DIS ((uint32_t)(EDMAC_COMPARE_SKIP_EN))                           /**<                 */
#define EDMAC_PRELOAD_DIS (((uint32_t)1 << 13))                                              /**<                        */
#define EDMAC_PRELOAD_EN ((uint32_t)(~EDMAC_PRELOAD_DIS))                                    /**<                     */
#define EDMAC_MEM_TRANS_CRC_EN (((uint32_t)1 << 12))                                         /**<                                            */
#define EDMAC_MEM_TRANS_CRC_DIS ((uint32_t)(~EDMAC_MEM_TRANS_CRC_EN))                        /**<                                            */
#define EDMAC_PERIPHERAL_NUMBER_MASK ((uint32_t)(0xFFFFF0FF))                                /**<                                            */
#define EDMAC_PERIPHERAL_NUMBER_SHIFT_MASK ((uint8_t)(1 << 8))                               /**<                                            */
#define EDMAC_PERIPHERAL_TYPE_SPI1 ((uint8_t)(0x00 << EDMAC_PERIPHERAL_NUMBER_SHIFT_MASK))   /**< EDAMC                       */
#define EDMAC_PERIPHERAL_TYPE_SPI2 ((uint8_t)( (uint32_t)1 << EDMAC_PERIPHERAL_NUMBER_SHIFT_MASK))   /**<                         */
#define EDMAC_PERIPHERAL_TYPE_USI1 ((uint8_t)(0x02 << EDMAC_PERIPHERAL_NUMBER_SHIFT_MASK))   /**< EDAMC?��:USI1                             */
#define EDMAC_PERIPHERAL_TYPE_USI3 ((uint8_t)(0x04 << EDMAC_PERIPHERAL_NUMBER_SHIFT_MASK))   /**< EDAMC?��:USI3                             */
#define EDMAC_PERIPHERAL_TYPE_USI2 ((uint8_t)(0x03 << EDMAC_PERIPHERAL_NUMBER_SHIFT_MASK))   /**< EDAMC?��:USI2                             */
#define EDMAC_PERIPHERAL_TYPE_AES ((uint8_t)(0x05 << EDMAC_PERIPHERAL_NUMBER_SHIFT_MASK))    /**< EDAMC?��:AES                              */
#define EDMAC_PERIPHERAL_TYPE_DES ((uint8_t)(0x06 << EDMAC_PERIPHERAL_NUMBER_SHIFT_MASK))    /**< EDAMC?��:DES                              */
#define EDMAC_PERIPHERAL_TYPE_SM1 ((uint8_t)(0x07 << EDMAC_PERIPHERAL_NUMBER_SHIFT_MASK))    /**< EDAMC?��:SM1                              */
#define EDMAC_PERIPHERAL_TYPE_SCI1 ((uint8_t)(0x08 << EDMAC_PERIPHERAL_NUMBER_SHIFT_MASK))   /**< EDAMC?��:SCI1                             */
#define EDMAC_PERIPHERAL_TYPE_SMS4 ((uint8_t)(0x09 << EDMAC_PERIPHERAL_NUMBER_SHIFT_MASK))   /**< EDAMC?��:SM4                              */
#define EDMAC_PERIPHERAL_TYPE_SHA ((uint8_t)(0x0A << EDMAC_PERIPHERAL_NUMBER_SHIFT_MASK))    /**< EDAMC?��:SHA                              */
#define EDMAC_PERIPHERAL_TYPE_SSF33 ((uint8_t)(0x0B << EDMAC_PERIPHERAL_NUMBER_SHIFT_MASK))  /**< EDAMC?��:SSF33                            */
#define EDMAC_PERIPHERAL_TYPE_CRYPTO ((uint8_t)(0x0C << EDMAC_PERIPHERAL_NUMBER_SHIFT_MASK)) /**< EDAMC?��:CRYPTO                           */
#define EDMAC_PERIPHERAL_TYPE_SCI2 ((uint8_t)(0x0D << EDMAC_PERIPHERAL_NUMBER_SHIFT_MASK))   /**< EDAMC?��:SCI2                             */
#define EDMAC_PERIPHERAL_TYPE_SPI3 ((uint8_t)(0x0E << EDMAC_PERIPHERAL_NUMBER_SHIFT_MASK))   /**< EDAMC?��:SPI3                             */

#define EDMAC_CHANNEL_PERIPHERAL_SPI1 ((uint8_t)(0x00))                                       /**< EDAMC?��:edmac1                       */
#define EDMAC_CHANNEL_PERIPHERAL_SPI2 ((uint8_t)( (uint32_t)1))                                       /**< EDAMC?��:edmac2                       */
#define EDMAC_CHANNEL_PERIPHERAL_USI1 ((uint8_t)(0x02))                                       /**< EDAMC?��:USI1                         */
#define EDMAC_CHANNEL_PERIPHERAL_USI2 ((uint8_t)(0x03))                                       /**< EDAMC?��:USI2                         */
#define EDMAC_CHANNEL_PERIPHERAL_AES ((uint8_t)(0x05))                                        /**< EDAMC?��:AES                          */
#define EDMAC_CHANNEL_PERIPHERAL_DES ((uint8_t)(0x06))                                        /**< EDAMC?��:DES                          */
#define EDMAC_CHANNEL_PERIPHERAL_SM1 ((uint8_t)(0x07))                                        /**< EDAMC?��:SM1                          */
#define EDMAC_CHANNEL_PERIPHERAL_UART1 ((uint8_t)(0x08))                                      /**< EDAMC?��:SCI1                         */
#define EDMAC_CHANNEL_PERIPHERAL_SMS4 ((uint8_t)(0x09))                                       /**< EDAMC?��:SM4                          */
#define EDMAC_CHANNEL_PERIPHERAL_SHA ((uint8_t)(0x0A))                                        /**< EDAMC?��:SHA                          */
#define EDMAC_CHANNEL_PERIPHERAL_UART3 ((uint8_t)(0x0B))                                      /**< EDAMC?��:SSF33                        */
#define EDMAC_CHANNEL_PERIPHERAL_CRYPTO ((uint8_t)(0x0C))                                     /**< EDAMC?��:CRYPTO                       */
#define EDMAC_CHANNEL_PERIPHERAL_UART2 ((uint8_t)(0x0D))                                      /**< EDAMC?��:SCI2                         */
#define EDMAC_CHANNEL_PERIPHERAL_SPI3 ((uint8_t)(0x0E))                                       /**< EDAMC?��:SPI3                         */
#define EDMAC_CHANNEL_PERIPHERAL_ZUC ((uint8_t)(0x0F))                                        /**< EDAMC?��:SPI3                         */
#define EDMAC_START_IT_EN (((uint32_t)1 << 7))                                                /**< EDMAC?????��?:???                     */
#define EDMAC_START_IT_DIS ((uint32_t)(~(1 << EDMAC_START_IT_EN)))                            /**< EDMAC????��? ???                     */
#define EDMAC_DIR_MASK ((uint32_t)(0xFFFFFF9F))                                               /**< */
#define EDMAC_DIR_SHIFT_MASK ((uint8_t)(1 << 5))                                              /**< */
#define EDMAC_TTYPE_SRAM_TO_SRAM ((uint8_t)(0x00 << EDMAC_DIR_SHIFT_MASK))                    /**< EDMAC????????:??RAM??RAM               */
#define EDMAC_TTYPE_PERIPHERAL_TO_SRAM ((uint8_t)( (uint32_t)1 << EDMAC_DIR_SHIFT_MASK))              /**< EDMAC????????:???��??RAM              */
#define EDMAC_TTYPE_SRAM_TO_PERIPHERAL ((uint8_t)(0x02 << EDMAC_DIR_SHIFT_MASK))              /**< EDMAC????????:??RAM???��              */
#define EDMAC_TTYPE_BOTH ((uint8_t)(0x03 << EDMAC_DIR_SHIFT_MASK))                            /**< EDMAC????????:??RAM???��?????��??RAM */
#define EDMAC_DIR_SRAM_TO_SRAM ((uint8_t)(1 << 0x00))                                         /**< EDMAC????????:??RAM??RAM               */
#define EDMAC_DIR_PERIPHERAL_TO_SRAM ((uint8_t)(1 << 0x01))                                   /**< EDMAC????????:???��??RAM              */
#define EDMAC_DIR_SRAM_TO_PERIPHERAL ((uint8_t)(1 << 0x02))                                   /**< EDMAC????????:??RAM???��              */
#define EDMAC_DIR_BOTH ((uint8_t)(1 << 0x03))                                                 /**< EDMAC????????:??RAM???��?????��??RAM */
#define EDMAC_SPI_FIFO_PRELOAD_MASK ((uint32_t)(0xFFFFFFF3))                                  /**<                                        */
#define EDMAC_SPI_FIFO_PRELOAD_SHIFT_MASK ((uint8_t)(1 << 2))                                 /**<                                        */
#define EDMAC_SPI_FIFO_PRELOAD_NOT ((uint32_t)(0x00 << EDMAC_SPI_FIFO_PRELOAD_SHIFT_MASK))    /**<                                        */
#define EDMAC_SPI_FIFO_PRELOAD_2BYTES ((uint32_t)( (uint32_t)1 << EDMAC_SPI_FIFO_PRELOAD_SHIFT_MASK)) /**<                                        */
#define EDMAC_SPI_FIFO_PRELOAD_4BYTES ((uint32_t)(0x02 << EDMAC_SPI_FIFO_PRELOAD_SHIFT_MASK)) /**<                                        */
#define EDMAC_SPI_FIFO_PRELOAD_8BYTES ((uint32_t)(0x03 << EDMAC_SPI_FIFO_PRELOAD_SHIFT_MASK)) /**<                                        */

#define EDMAC_VALID_FLAG (((uint32_t)1 << 1))                             /**< EDAMC VALID???                        */
#define EDMAC_UNVALID_FLAG ((uint32_t)(~(1 << EDMAC_VALID_FLAG)))         /**< EDMAC UNVALID???                      */
#define EDMAC_MIN_DONE_IT_EN (((uint32_t)1 << 0))                         /**<                                        */
#define EDMAC_MIN_DONE_IT_DIS ((uint32_t) ~((1 << EDMAC_MIN_DONE_IT_EN))) /**<                                        */

/*EDMACCSR*/
#define EDMAC_SSF_SPI1_FLAG (((uint32_t)1 << 31)) /**< EDAMC SPI SS ��                        */
#define EDMAC_SSF_SPI2_FLAG (((uint32_t)1 << 30)) /**< EDAMC SPI SS ��                        */
#define EDMAC_SSF_SPI3_FLAG (((uint32_t)1 << 29)) /**< EDAMC SPI SS ��                        */
#define EDMAC_SSF_SPI4_FLAG (((uint32_t)1 << 28)) /**< EDAMC SPI SS ��                        */

#define EDMAC_EN (((uint32_t)1 << 16))           /**< EDAMC */
#define EDMAC_DIS ((uint32_t)(~(1 << EDMAC_EN))) /**< EDAMC */
#define EDMAC_FLAG_FAIL (((uint32_t)1 << 15))    /**< EDAMC                                  */
#define EDMAC_FLAG_SCHNUM (((uint32_t)1 << 7))   /**< EDAMC */
#define EDMAC_FLAG_DCHNUM (((uint32_t)1 << 6))   /**< EDAMC */
#define EDMAC_FLAG_MAJ_DONE (((uint32_t)1 << 3)) /**< EDMAC                                  */
#define EDMAC_FLAG_START (((uint32_t)1 << 2))    /**< EDMAC                                  */
#define EDMAC_FLAG_MIN_DONE (((uint32_t)1 << 1)) /**< EDMAC                                  */
#define EDMAC_FLAG_BUSY (((uint32_t)1 << 0))     /**< EDMAC                                  */
/*EDMACRBAR*/
#define EDMAC_READ_BUFFER_INC_EN (((uint32_t)1 << 31))                           /**< */
#define EDMAC_READ_BUFFER_INC_DIS ((uint32_t)(~(1 << EDMAC_READ_BUFFER_INC_EN))) /**< */
#define EDMAC_READ_BUFFER_DEC_EN (((uint32_t)1 << 30))                           /**<*/
#define EDMAC_READ_BUFFER_DEC_DIS ((uint32_t)(~(1 << EDMAC_READ_BUFFER_DEC_EN))) /**<*/
#define EDMAC_READ_BUFFER_BASE_ADD_MASK ((uint32_t)(0xFFF00000))                 /**<                                        */
#define EDMAC_READ_BUFFER_BASE_ADD_SHIFTMASK ((uint8_t)(1 << 0))                 /**<                                        */
/*EDMACWBAR*/
#define EDMAC_WRITE_BUFFER_INC_EN (((uint32_t)1 << 31))                            /**<*/
#define EDMAC_WRITE_BUFFER_INC_DIS ((uint32_t)(~(1 << EDMAC_WRITE_BUFFER_INC_EN))) /**<*/
#define EDMAC_WRITE_BUFFER_DEC_EN (((uint32_t)1 << 30))                            /**< */
#define EDMAC_WRITE_BUFFER_DEC_DIS ((uint32_t)(~(1 << EDMAC_WRITE_BUFFER_DEC_EN))) /**< */
#define EDMAC_WRITE_BUFFER_BASE_ADD_MASK ((uint32_t)(0xFFF00000))                  /**<                                        */
#define EDMAC_WRITE_BUFFER_BASE_ADD_SHIFTMASK ((uint8_t)(1 << 0))

#define EDMAC_MINOR_TRANSFER_DATA_SUM_MASK ((uint32_t)(0xFFF00000))   /**<                                        */
#define EDMAC_MINOR_TRANSFER_DATA_SUM_SHIFT_MASK (((uint32_t)1 << 0)) /**<                                        */
#define EDMAC_MINOR_TRANSFER_DATA_CNT_MASK ((uint32_t)(0xFFF00000))   /**<                                        */
#define EDMAC_MINOR_TRANSFER_DATA_CNT_SHIFT_MASK (((uint32_t)1 << 0)) /**<                                        */
#define EDMAC_MAJOR_TRANSFER_DATA_SUM_MASK ((uint32_t)(0xFFF00000))   /**<                                        */
#define EDMAC_MAJOR_TRANSFER_DATA_SUM_SHIFT_MASK (((uint32_t)1 << 0)) /**<                                        */
#define EDMAC_MAJOR_TRANSFER_DATA_CNT_MASK ((uint32_t)(0xFFF00000))   /**<                                        */
#define EDMAC_MAJOR_TRANSFER_DATA_CNT_SHIFT_MASK (((uint32_t)1 << 0)) /**<                                        */
#define EDMAC_PERIPHERAL_ADD_MASK ((uint32_t)(0xFFFF0000))            /**<                                        */
#define EDMAC_PERIPHERAL_ADD_SHIFT_MASK (((uint32_t)1 << 0))          /**<                                        */

/*EDMACRBARSTEP*/
#define EDMAC_READ_BUFFER_ADD_STEP_EN (((uint32_t)1 << 31))
#define EDMAC_READ_BUFFER_ADD_DECREASE (((uint32_t)1 << 30))
#define EDMAC_READ_BUFFER_ADD_STEP_MASK ((uint32_t)(0xFFFF0000))  /**<                                        */
#define EDMAC_READ_BUFFER_ADD_STEP_SHIFTMASK (((uint32_t)1 << 0)) /**<                                        */
/*EDMACWBARSTEP*/
#define EDMAC_WRITE_BUFFER_ADD_STEP_EN (((uint32_t)1 << 31))
#define EDMAC_WRITE_BUFFER_ADD_DECREASE (((uint32_t)1 << 30))
#define EDMAC_WRITE_BUFFER_ADD_STEP_MASK ((uint32_t)(0xFFFF0000))  /**<                                        */
#define EDMAC_WRITE_BUFFER_ADD_STEP_SHIFTMASK (((uint32_t)1 << 0)) /**<                                        */
/*LASTMINSUMR*/
#define EDMAC_LAST_MINUM_SUM_EN (((uint32_t)1 << 31))
#define EDMAC_LAST_MINUM_SUM_MASK ((uint32_t)(0xFFFF0000)) /**<                                        */
#define EDMAC_WRITE_BUFFER_ADD_STEP_SHIFTMASK (((uint32_t)1 << 0))

#endif /* end __EDMAC__ */

#define __EPORT__
#ifdef __EPORT__
/*** EPORT **********************************************/
/*EPPAR*/
#define EPORT_EPPAR_EPPA0 (0)  /**<  */
#define EPORT_EPPAR_EPPA1 (2)  /**<  */
#define EPORT_EPPAR_EPPA2 (4)  /**<  */
#define EPORT_EPPAR_EPPA3 (6)  /**<  */
#define EPORT_EPPAR_EPPA4 (8)  /**<  */
#define EPORT_EPPAR_EPPA5 (10) /**<  */
#define EPORT_EPPAR_EPPA6 (12) /**<  */
#define EPORT_EPPAR_EPPA7 (14) /**<  */

/*EPDDR*/
#define EPORT_EPDDR_EPDD (0)          /**<  */
#define EPORT_EPDDR_EPDD0 ( (uint32_t)1 << 0) /**<  */
#define EPORT_EPDDR_EPDD1 ( (uint32_t)1 << 1) /**<  */
#define EPORT_EPDDR_EPDD2 ( (uint32_t)1 << 2) /**<  */
#define EPORT_EPDDR_EPDD3 ( (uint32_t)1 << 3) /**<  */
#define EPORT_EPDDR_EPDD4 ( (uint32_t)1 << 4) /**<  */
#define EPORT_EPDDR_EPDD5 ( (uint32_t)1 << 5) /**<  */
#define EPORT_EPDDR_EPDD6 ( (uint32_t)1 << 6) /**<  */
#define EPORT_EPDDR_EPDD7 ( (uint32_t)1 << 7) /**<  */

/*EPIER*/
#define EPORT_EPIER_EPIE (0)          /**<  */
#define EPORT_EPIER_EPIE0 ( (uint32_t)1 << 0) /**<  */
#define EPORT_EPIER_EPIE1 ( (uint32_t)1 << 1) /**<  */
#define EPORT_EPIER_EPIE2 ( (uint32_t)1 << 2) /**<  */
#define EPORT_EPIER_EPIE3 ( (uint32_t)1 << 3) /**<  */
#define EPORT_EPIER_EPIE4 ( (uint32_t)1 << 4) /**<  */
#define EPORT_EPIER_EPIE5 ( (uint32_t)1 << 5) /**<  */
#define EPORT_EPIER_EPIE6 ( (uint32_t)1 << 6) /**<  */
#define EPORT_EPIER_EPIE7 ( (uint32_t)1 << 7) /**<  */

/*EPDR*/
#define EPORT_EPDR_EPD (0)          /**<  */
#define EPORT_EPDR_EPD0 ( (uint32_t)1 << 0) /**<  */
#define EPORT_EPDR_EPD1 ( (uint32_t)1 << 1) /**<  */
#define EPORT_EPDR_EPD2 ( (uint32_t)1 << 2) /**<  */
#define EPORT_EPDR_EPD3 ( (uint32_t)1 << 3) /**<  */
#define EPORT_EPDR_EPD4 ( (uint32_t)1 << 4) /**<  */
#define EPORT_EPDR_EPD5 ( (uint32_t)1 << 5) /**<  */
#define EPORT_EPDR_EPD6 ( (uint32_t)1 << 6) /**<  */
#define EPORT_EPDR_EPD7 ( (uint32_t)1 << 7) /**<  */

/*EPPDR*/
#define EPORT_EPPDR_EPPD (0)          /**<  */
#define EPORT_EPPDR_EPPD0 ( (uint32_t)1 << 0) /**<  */
#define EPORT_EPPDR_EPPD1 ( (uint32_t)1 << 1) /**<  */
#define EPORT_EPPDR_EPPD2 ( (uint32_t)1 << 2) /**<  */
#define EPORT_EPPDR_EPPD3 ( (uint32_t)1 << 3) /**<  */
#define EPORT_EPPDR_EPPD4 ( (uint32_t)1 << 4) /**<  */
#define EPORT_EPPDR_EPPD5 ( (uint32_t)1 << 5) /**<  */
#define EPORT_EPPDR_EPPD6 ( (uint32_t)1 << 6) /**<  */
#define EPORT_EPPDR_EPPD7 ( (uint32_t)1 << 7) /**<  */

/*EPFR*/
#define EPORT_EPFR_EPF (0)          /**<  */
#define EPORT_EPFR_EPF0 ( (uint32_t)1 << 0) /**<  */
#define EPORT_EPFR_EPF1 ( (uint32_t)1 << 1) /**<  */
#define EPORT_EPFR_EPF2 ( (uint32_t)1 << 2) /**<  */
#define EPORT_EPFR_EPF3 ( (uint32_t)1 << 3) /**<  */
#define EPORT_EPFR_EPF4 ( (uint32_t)1 << 4) /**<  */
#define EPORT_EPFR_EPF5 ( (uint32_t)1 << 5) /**<  */
#define EPORT_EPFR_EPF6 ( (uint32_t)1 << 6) /**<  */
#define EPORT_EPFR_EPF7 ( (uint32_t)1 << 7) /**<  */

/*EPPUER*/
#define EPORT_EPPUER_EPPUE (0)          /**<  */
#define EPORT_EPPUER_EPPUE0 ( (uint32_t)1 << 0) /**<  */
#define EPORT_EPPUER_EPPUE1 ( (uint32_t)1 << 1) /**<  */
#define EPORT_EPPUER_EPPUE2 ( (uint32_t)1 << 2) /**<  */
#define EPORT_EPPUER_EPPUE3 ( (uint32_t)1 << 3) /**<  */
#define EPORT_EPPUER_EPPUE4 ( (uint32_t)1 << 4) /**<  */
#define EPORT_EPPUER_EPPUE5 ( (uint32_t)1 << 5) /**<  */
#define EPORT_EPPUER_EPPUE6 ( (uint32_t)1 << 6) /**<  */
#define EPORT_EPPUER_EPPUE7 ( (uint32_t)1 << 7) /**<  */

/*EPLPR*/
#define EPORT_EPLPR_EPLP (0)          /**<  */
#define EPORT_EPLPR_EPLP0 ( (uint32_t)1 << 0) /**<  */
#define EPORT_EPLPR_EPLP1 ( (uint32_t)1 << 1) /**<  */
#define EPORT_EPLPR_EPLP2 ( (uint32_t)1 << 2) /**<  */
#define EPORT_EPLPR_EPLP3 ( (uint32_t)1 << 3) /**<  */
#define EPORT_EPLPR_EPLP4 ( (uint32_t)1 << 4) /**<  */
#define EPORT_EPLPR_EPLP5 ( (uint32_t)1 << 5) /**<  */
#define EPORT_EPLPR_EPLP6 ( (uint32_t)1 << 6) /**<  */
#define EPORT_EPLPR_EPLP7 ( (uint32_t)1 << 7) /**<  */

/*EPODER*/
#define EPORT_EPODER_EPODE (0)          /**<  */
#define EPORT_EPODER_EPODE0 ( (uint32_t)1 << 0) /**<  */
#define EPORT_EPODER_EPODE1 ( (uint32_t)1 << 1) /**<  */
#define EPORT_EPODER_EPODE2 ( (uint32_t)1 << 2) /**<  */
#define EPORT_EPODER_EPODE3 ( (uint32_t)1 << 3) /**<  */
#define EPORT_EPODER_EPODE4 ( (uint32_t)1 << 4) /**<  */
#define EPORT_EPODER_EPODE5 ( (uint32_t)1 << 5) /**<  */
#define EPORT_EPODER_EPODE6 ( (uint32_t)1 << 6) /**<  */
#define EPORT_EPODER_EPODE7 ( (uint32_t)1 << 7) /**<  */

#endif

#define __I2C__
#ifdef __I2C__

/*** I2C **********************************************/
/*I2C*/
/*I2CC*/
#define I2C_EN (1 << 0)                          /**< I2C module enable*/
#define I2C_DIS (0xFE)                           /**< I2C module disable*/
#define I2C_EN_IT (1 << 1)                       /**< I2C interrupt enable*/
#define I2C_DIS_IT (0xFD)                        /**< I2C interrupt disable*/
#define I2C_MASTER (1 << 2)                      /**< I2C master mode*/
#define I2C_SLAVE (0xFB)                         /**< I2C slave mode*/
#define I2C_EN_ACK (1 << 3)                      /**< I2C active enable*/
#define I2C_DIS_ACK (0xF7)                       /**< I2C active disable*/
#define I2C_EN_REPEAT_START (1 << 4)             /**< I2C repeat start signal enable*/
#define I2C_DIS_REPEAT_START (0xEF)              /**< I2C repeat start signal disable*/
#define I2C_EN_ADDRESS_MATCH_IT (1 << 5)         /**< I2C address match interrpt enable*/
#define I2C_DIS_ADDRESS_MATCH_IT (0xDF)          /**< I2C address match interrpt disable*/
#define I2C_EN_HIGH_SPEED_MODE (1 << 6)          /**< I2C high speed enable*/
#define I2C_DIS_HIGH_SPEED_MODE (0xBF)           /**< I2C high speed disable*/
#define I2C_EN_SLAVE_HIGH_SPEED_MODE_IT (1 << 7) /**< I2C high speed interrupt enable*/
#define I2C_DIS_SLAVE_HIGH_SPEED_MODE_IT (0x7F)  /**< I2C high speed interrupt disable*/
/*I2CP*/
#define I2C_CLOCK_MODE_TEST (1 << 6)                 /**< I2C  clock test mode*/
#define I2C_CLOCK_MODE_NORMAL (~I2C_CLOCK_MODE_TEST) /**< I2C  clock normal mode*/
/*I2CS*/
#define I2C_FLAG_TF (1 << 0)    /**< I2C TF*/
#define I2C_FLAG_RC (1 << 1)    /**< I2C RC*/
#define I2C_FLAG_AASLV (1 << 2) /**< I2C AASLV*/
#define I2C_FLAG_BUSY (1 << 3)  /**< I2C BUSY*/
#define I2C_FLAG_ARBL (1 << 4)  /**< I2C ARBL*/
#define I2C_FLAG_RXTX (1 << 5)  /**< I2C RXTX*/
#define I2C_FLAG_DACK (1 << 6)  /**< I2C DACK*/
#define I2C_FLAG_AACK (1 << 7)  /**< I2C DACK*/
#define I2C_FLAG_RX_MASK (0)    /**< I2C RX*/
#define I2C_FLAG_TX_MASK (0x20) /**< I2C TX*/

/*I2CSHIR*/
#define I2C_FLAG_SLAVE_HIGH_SPEED (1 << 0) /**<           */
/*I2CSHT*/
#define I2C_EN_SDA_FILTER (1 << 6) /**<          */
#define I2C_EN_SCL_FILTER (1 << 7) /**<          */
/**/
#define I2C_SLAVE_HIGH_SPEED (1 << 0) /**<           */
/*I2PCR*/
#define I2C_PIN_SCL (0) /**< I2C SCL     */
#define I2C_PIN_SDA (1) /**< I2C SDA     */
#define I2C_PA_SHIFT_MASK (6)
#define I2C_WOM_SHIFT_MASK (4)
#define I2C_PD_SHIFT_MASK (2)
#define I2C_PU_SHIFT_MASK (0)
#define I2C_PIN_SDA_GPIO (0x80)                                /**< SDA GPIO funtion */
#define I2C_PIN_SDA_PRIMARY_FUN (~(I2C_PIN_SDA_GPIO))          /**< SDA for main-funtion*/
#define I2C_PIN_SCL_GPIO (0x40)                                /**< SCL for GPIO funtion */
#define I2C_PIN_SCL_PRIMARY_FUN (~(I2C_PIN_SCL_GPIO))          /**< SCL for main-funtion*/
#define I2C_PIN_SDA_OPEN_DRAIN_MODE (0x20)                     /**< I2C SDA open-drain output */
#define I2C_PIN_SDA_CMOS_MODE (~(I2C_PIN_SDA_OPEN_DRAIN_MODE)) /**< I2C SDA CMOS output */
#define I2C_PIN_SCL_OPEN_DRAIN_MODE (0x10)                     /**< I2C SCL open-drain output */
#define I2C_PIN_SCL_CMOS_MODE (~(I2C_PIN_SCL_OPEN_DRAIN_MODE)) /**< I2C SDA CMOS output */
#define I2C_PIN_SDA_EN_PULLDOWN (0x04)                         /**< I2C SDA pulldown enable */
#define I2C_PIN_SDA_DIS_PULLDOWN (~(I2C_PIN_SDA_EN_PULLDOWN))  /**< I2C SDA pulldown disable */
#define I2C_PIN_SCL_EN_PULLDOWN (0x02)                         /**< I2C SCL pulldown enable */
#define I2C_PIN_SCL_DIS_PULLDOWN (~(I2C_PIN_SCL_EN_PULLDOWN))  /**< I2C SCL pulldown disable */
#define I2C_PIN_SDA_EN_PULLUP (0x02)                           /**< I2C SDA pullup enable */
#define I2C_PIN_SDA_DIS_PULLUP (~(I2C_PIN_SDA_EN_PULLUP))      /**< I2C SDA pullup disable*/
#define I2C_PIN_SCL_EN_PULLUP ( (uint32_t)1)                           /**< I2C SCL pullup enable*/
#define I2C_PIN_SCL_DIS_PULLUP (~(I2C_PIN_SCL_EN_PULLUP))      /**< I2C SCL pullup disable*/
/*I2CPDR*/
#define I2C_PIN_SCL_DIR_GPIO_OUT (1 << 0)                     /**< I2C SCL direction output*/
#define I2C_PIN_SCL_DIR_GPIO_IN (~(I2C_PIN_SCL_DIR_GPIO_OUT)) /**< I2C SCL direction interrupt*/
#define I2C_PIN_SDA_DIR_GPIO_OUT (1 << 1)                     /**< I2C SDA direction output*/
#define I2C_PIN_SDA_DIR_GPIO_IN (~(I2C_PIN_SDA_DIR_GPIO_OUT)) /**< I2C SDA direction interrupt*/
#endif                                                        
/* end __I2C__ */

#define __IO_CONTROL__
#ifdef __IO_CONTROL__
/*** IO_CONTROL **********************************************/
/*SPICR*/
#define IOCTRL_SPICR_SPI1_PS (8)           /**<  */
#define IOCTRL_SPICR_MISO1_PS ( (uint32_t)1 << 8)  /**<  */
#define IOCTRL_SPICR_MOSI1_PS ( (uint32_t)1 << 9)  /**<  */
#define IOCTRL_SPICR_SCK1_PS ( (uint32_t)1 << 10)  /**<  */
#define IOCTRL_SPICR_SS1_PS ( (uint32_t)1 << 11)   /**<  */
#define IOCTRL_SPICR_SPI1_IE (12)          /**<  */
#define IOCTRL_SPICR_MISO1_IE ( (uint32_t)1 << 12) /**<  */
#define IOCTRL_SPICR_MOSI1_IE ( (uint32_t)1 << 13) /**<  */
#define IOCTRL_SPICR_SCK1_IE ( (uint32_t)1 << 14)  /**<  */
#define IOCTRL_SPICR_SS1_IE ( (uint32_t)1 << 15)   /**<  */
#define IOCTRL_SPICR_SPI2_PS (16)          /**<  */
#define IOCTRL_SPICR_MISO2_PS ( (uint32_t)1 << 16) /**<  */
#define IOCTRL_SPICR_MOSI2_PS ( (uint32_t)1 << 17) /**<  */
#define IOCTRL_SPICR_SCK2_PS ( (uint32_t)1 << 18) /**<  */
#define IOCTRL_SPICR_SS2_PS ( (uint32_t)1 << 19)   /**<  */
#define IOCTRL_SPICR_SPI2_IE (20)          /**<  */
#define IOCTRL_SPICR_MISO2_IE ( (uint32_t)1 << 20) /**<  */
#define IOCTRL_SPICR_MOSI2_IE ( (uint32_t)1 << 21) /**<  */
#define IOCTRL_SPICR_SCK2_IE ( (uint32_t)1 << 22)  /**<  */
#define IOCTRL_SPICR_SS2_IE ( (uint32_t)1 << 23)   /**<  */
#define IOCTRL_SPICR_SPI3_PS (24)          /**<  */
#define IOCTRL_SPICR_MISO3_PS ( (uint32_t)1 << 24) /**<  */
#define IOCTRL_SPICR_MOSI3_PS ( (uint32_t)1 << 25) /**<  */
#define IOCTRL_SPICR_SCK3_PS ( (uint32_t)1 << 26) /**<  */
#define IOCTRL_SPICR_SS3_PS ( (uint32_t)1 << 27)   /**<  */
#define IOCTRL_SPICR_SPI3_IE (28)          /**<  */
#define IOCTRL_SPICR_MISO3_IE ( (uint32_t)1 << 28) /**<  */
#define IOCTRL_SPICR_MOSI3_IE ( (uint32_t)1 << 29) /**<  */
#define IOCTRL_SPICR_SCK3_IE ( (uint32_t)1 << 30)  /**<  */
#define IOCTRL_SPICR_SS3_IE ( (uint32_t)1 << 31)   /**<  */

/*USICR*/
#define IOCTRL_USICR_DS1_DS0 (0x03 << 0)       /**<  */
#define IOCTRL_USICR_DS0 ( (uint32_t)1 << 0)           /**<  */
#define IOCTRL_USICR_DS1 ( (uint32_t)1 << 1)           /**<  */
#define IOCTRL_USICR_SR ( (uint32_t)1 << 2)            /**<  */
#define IOCTRL_USICR_IS ( (uint32_t)1 << 3)            /**<  */
#define IOCTRL_USICR_USI1_PS (8)               /**<  */
#define IOCTRL_USICR_ISORST1_PS ( (uint32_t)1 << 8)    /**<  */
#define IOCTRL_USICR_ISODAT1_PS ( (uint32_t)1 << 9)    /**<  */
#define IOCTRL_USICR_ISO1_PS ( (uint32_t)1 << 10)   /**<  */
#define IOCTRL_USICR_USI2_PUEN (16)            /**<  */
#define IOCTRL_USICR_ISORST2_PUEN ( (uint32_t)1 << 16) /**<  */
#define IOCTRL_USICR_ISODAT2_PUEN ( (uint32_t)1 << 17) /**<  */
#define IOCTRL_USICR_ISOCLK2_PUEN ( (uint32_t)1 << 18) /**<  */
#define IOCTRL_USICR_USI2_DIEN (20)            /**<  */
#define IOCTRL_USICR_ISORST2_DIEN ( (uint32_t)1 << 20) /**<  */
#define IOCTRL_USICR_ISODAT2_DIEN ( (uint32_t)1 << 21) /**<  */
#define IOCTRL_USICR_ISOCLK2_DIEN ( (uint32_t)1 << 22) /**<  */

/*I2CCR*/
#define IOCTRL_I2CCR_DS1_DS0 (0x03 << 0)  /**<  */
#define IOCTRL_I2CCR_DS0 ( (uint32_t)1 << 0)      /**<  */
#define IOCTRL_I2CCR_DS1 ( (uint32_t)1 << 1)      /**<  */
#define IOCTRL_I2CCR_SR ( (uint32_t)1 << 2)       /**<  */
#define IOCTRL_I2CCR_IS ( (uint32_t)1 << 3)       /**<  */
#define IOCTRL_I2CCR_I2C1_PS (8)          /**<  */
#define IOCTRL_I2CCR_SCL1_PS ( (uint32_t)1 << 8)  /**<  */
#define IOCTRL_I2CCR_SDA1_PS ( (uint32_t)1 << 9)  /**<  */
#define IOCTRL_I2CCR_I2C1_IE (12)         /**<  */
#define IOCTRL_I2CCR_SCL1_IE ( (uint32_t)1 << 12) /**<  */
#define IOCTRL_I2CCR_SDA1_IE ( (uint32_t)1 << 13) /**<  */


/*UARTCR*/
#define IOCTRL_UARTCR_DS1_DS0 (0x03 << 0)            /**<  */
#define IOCTRL_UARTCR_DS0 ( (uint32_t)1 << 0)                /**<  */
#define IOCTRL_UARTCR_DS1 ( (uint32_t)1 << 1)                /**<  */
#define IOCTRL_UARTCR_SR ( (uint32_t)1 << 2)                 /**<  */
#define IOCTRL_UARTCR_IS ( (uint32_t)1 << 3)                 /**<  */
#define IOCTRL_UARTCR_RXD1_PS ( (uint32_t)1 << 8)            /**<  */
#define IOCTRL_UARTCR_UART1_PS (8)                  /**<  */
#define IOCTRL_UARTCR_TXD1_PS ( (uint32_t)1 << 9)            /**<  */
#define IOCTRL_UARTCR_CTS1_PUE ( (uint32_t)1 << 11)          /**<  */
#define IOCTRL_UARTCR_UART3_PS (12)                  /**<  */
#define IOCTRL_UARTCR_RXD3_PS ( (uint32_t)1 << 12)           /**<  */
#define IOCTRL_UARTCR_TXD3_PS ( (uint32_t)1 << 13)           /**<  */
#define IOCTRL_UARTCR_CTS3_PUE ( (uint32_t)1 << 15)          /**<  */
#define IOCTRL_UARTCR_UART2_PS (16)                  /**<  */
#define IOCTRL_UARTCR_RXD2_PS ( (uint32_t)1 << 16)           /**<  */
#define IOCTRL_UARTCR_TXD2_PS ( (uint32_t)1 << 17)           /**<  */
#define IOCTRL_UARTCR_CTS2_PUE ( (uint32_t)1 << 19)          /**<  */
#define IOCTRL_UARTCR_GINT_SWAP_MASK (0x3F << 24)    /**<  */
#define IOCTRL_UARTCR_GINT_SWAP (24)                 /**<  */
#define IOCTRL_UARTCR_GINT_SWAP_BIT0 ( (uint32_t)1 << 24)    /**<  */
#define IOCTRL_UARTCR_GINT_SWAP_BIT1 ( (uint32_t)1 << 25)    /**<  */
#define IOCTRL_UARTCR_GINT_SWAP_BIT2 ( (uint32_t)1 << 26)    /**<  */
#define IOCTRL_UARTCR_GINT_SWAP_BIT3 ( (uint32_t)1 << 27)    /**<  */
#define IOCTRL_UARTCR_GINT_SWAP_BIT4 ( (uint32_t)1 << 28)    /**<  */
#define IOCTRL_UARTCR_GINT_SWAP_BIT5 ( (uint32_t)1 << 29)    /**<  */
#define IOCTRL_UARTCR_GINT_SWAP_LOAD_EN ( (uint32_t)1 << 31) /**<  */

/*GINTLCR*/
#define IOCTRL_GINTLCR_DS1_DS0 (0x03 << 0)   /**<  */
#define IOCTRL_GINTLCR_DS0 ( (uint32_t)1 << 0)       /**<  */
#define IOCTRL_GINTLCR_DS1 ( (uint32_t)1 << 1)       /**<  */
#define IOCTRL_GINTLCR_SR ( (uint32_t)1 << 2)        /**<  */
#define IOCTRL_GINTLCR_IS ( (uint32_t)1 << 3)        /**<  */
#define IOCTRL_GINTLCR_IE (16)               /**<  */
#define IOCTRL_GINTLCR_GINT0_IE ( (uint32_t)1 << 16) /**<  */
#define IOCTRL_GINTLCR_GINT1_IE ( (uint32_t)1 << 17) /**<  */
#define IOCTRL_GINTLCR_GINT2_IE ( (uint32_t)1 << 18) /**<  */
#define IOCTRL_GINTLCR_GINT3_IE ( (uint32_t)1 << 19) /**<  */
#define IOCTRL_GINTLCR_GINT4_IE ( (uint32_t)1 << 20) /**<  */
#define IOCTRL_GINTLCR_GINT5_IE ( (uint32_t)1 << 21) /**<  */
#define IOCTRL_GINTLCR_PS (24)               /**<  */
#define IOCTRL_GINTLCR_GINT0_PS ( (uint32_t)1 << 24) /**<  */
#define IOCTRL_GINTLCR_GINT1_PS ( (uint32_t)1 << 25) /**<  */
#define IOCTRL_GINTLCR_GINT2_PS ( (uint32_t)1 << 26) /**<  */
#define IOCTRL_GINTLCR_GINT3_PS ( (uint32_t)1 << 27) /**<  */
#define IOCTRL_GINTLCR_GINT4_PS ( (uint32_t)1 << 28) /**<  */
#define IOCTRL_GINTLCR_GINT5_PS ( (uint32_t)1 << 29) /**<  */

/*GINTHCR*/
#define IOCTRL_GINTHCR_DS1_DS0 (0x03 << 0)    /**<  */
#define IOCTRL_GINTHCR_DS0 ( (uint32_t)1 << 0)        /**<  */
#define IOCTRL_GINTHCR_DS1 ( (uint32_t)1 << 1)        /**<  */
#define IOCTRL_GINTHCR_SR ( (uint32_t)1 << 2)         /**<  */
#define IOCTRL_GINTHCR_IS ( (uint32_t)1 << 3)         /**<  */
#define IOCTRL_GINTHCR_IE (16)                /**<  */
#define IOCTRL_GINTHCR_GINT13_IE ( (uint32_t)1 << 21) /**<  */
#define IOCTRL_GINTHCR_GINT14_IE ( (uint32_t)1 << 22) /**<  */
#define IOCTRL_GINTHCR_GINT15_IE ( (uint32_t)1 << 23) /**<  */
#define IOCTRL_GINTHCR_PS (24)                /**<  */
#define IOCTRL_GINTHCR_GINT13_PS ( (uint32_t)1 << 29) /**<  */
#define IOCTRL_GINTHCR_GINT14_PS ( (uint32_t)1 << 30) /**<  */
#define IOCTRL_GINTHCR_GINT15_PS ( (uint32_t)1 << 31) /**<  */

/*SWAPCR*/
#define IOCTRL_SWAPCR_SWAP_BIT0 ( (uint32_t)1 << 0)   /**< 0:{ss3,sck3,miso3,mosi3}enable; 1:gint[8:11]enable */
#define IOCTRL_SWAPCR_SWAP_BIT1 ( (uint32_t)1 << 1)   /**< 0:gint[15:14] enable; 1:gint[15:14] disable*/
#define IOCTRL_SWAPCR_SWAP_BIT2 ( (uint32_t)1 << 2)   /**< 0:{txd2,rxd2} enable; 1:{txd2,rxd2} disable */
#define IOCTRL_SWAPCR_SWAP_BIT16 ( (uint32_t)1 << 16) /**< 0:{txd3,rxd3} enable; 1:{txd3,rxd3} disable  */
#define IOCTRL_SWAPCR_SWAP_BIT17 ( (uint32_t)1 << 17) /**< 0:gint[13] enable; 1:trace function enable  */
#define IOCTRL_SWAPCR_SWAP_BIT18 ( (uint32_t)1 << 18) /**< 0:gint[14] enable; 1:uart1_rts enable  */
#define IOCTRL_SWAPCR_SWAP_BIT19 ( (uint32_t)1 << 19) /**< 0:gint[15] enable; 1:uart1_cts enable  */
#define IOCTRL_SWAPCR_SWAP_BIT21 ( (uint32_t)1 << 21) /**< 0:gint[13] enable; 1:uart2_cts enable  */
#define IOCTRL_SWAPCR_SWAP_BIT24 ( (uint32_t)1 << 24) /**< 0:gint13 enable; 1:pwm0 enable  */
#define IOCTRL_SWAPCR_SWAP_BIT25 ( (uint32_t)1 << 25) /**< 0:gint14 enable; 1:pwm1 enable  */
#define IOCTRL_SWAPCR_SWAP_BIT26 ( (uint32_t)1 << 26) /**< 0:scl enable; 1:pwm2 enable  */
#define IOCTRL_SWAPCR_SWAP_BIT27 ( (uint32_t)1 << 27) /**< 0:sda enable; 1:pwm3 enable  */
#define IOCTRL_SWAPCR_SWAP_BIT28 ( (uint32_t)1 << 28) /**< 0:txd enable; 1:pwm4 enable  */
#define IOCTRL_SWAPCR_SWAP_BIT29 ( (uint32_t)1 << 29) /**< 0:rxd enable; 1:pwm5 enable  */
#define IOCTRL_SWAPCR_SWAP_BIT30 ( (uint32_t)1 << 30) /**< 0:txd2 enable; 1:pwm6 enable  */
#define IOCTRL_SWAPCR_SWAP_BIT31 ( (uint32_t)1 << 31) /**< 0:rxd2 enable; 1:pwm7 enable  */

/*SPIM1CR*/
#define IOCTRL_SPIM1CR_D_DS1_DS0 (0x03 << 0)   /**<  */
#define IOCTRL_SPIM1CR_D_DS0 ( (uint32_t)1 << 0)       /**<  */
#define IOCTRL_SPIM1CR_D_DS1 ( (uint32_t)1 << 1)       /**<  */
#define IOCTRL_SPIM1CR_D_SR ( (uint32_t)1 << 2)        /**<  */
#define IOCTRL_SPIM1CR_D_IS ( (uint32_t)1 << 3)        /**<  */
#define IOCTRL_SPIM1CR_PUE ( (uint32_t)1 << 4)         /**<  */
#define IOCTRL_SPIM1CR_ODE ( (uint32_t)1 << 5)         /**<  */
#define IOCTRL_SPIM1CR_SCK_DS1_DS0 (0x03 << 8) /**<  */
#define IOCTRL_SPIM1CR_SCK_DS0 ( (uint32_t)1 << 8)     /**<  */
#define IOCTRL_SPIM1CR_SCK_DS1 ( (uint32_t)1 << 9)     /**<  */
#define IOCTRL_SPIM1CR_SCK_SR ( (uint32_t)1 << 10)      /**<  */
#define IOCTRL_SPIM1CR_SCK_IS ( (uint32_t)1 << 11)      /**<  */
#define IOCTRL_SPIM1CR_SS_DS1_DS0 (0x03 << 12) /**<  */
#define IOCTRL_SPIM1CR_SS_DS0 ( (uint32_t)1 << 12)     /**<  */
#define IOCTRL_SPIM1CR_SS_DS1 ( (uint32_t)1 << 13)     /**<  */
#define IOCTRL_SPIM1CR_SS_SR ( (uint32_t)1 << 14)      /**<  */
#define IOCTRL_SPIM1CR_SS_IS ( (uint32_t)1 << 15)      /**<  */
#define IOCTRL_SPIM1CR_PS (16)                 /**<  */
#define IOCTRL_SPIM1CR_SS_PS ( (uint32_t)1 << 16)      /**<  */
#define IOCTRL_SPIM1CR_SCK_PS ( (uint32_t)1 << 17)     /**<  */
#define IOCTRL_SPIM1CR_D0_PS ( (uint32_t)1 << 18)      /**<  */
#define IOCTRL_SPIM1CR_D1_PS ( (uint32_t)1 << 19)      /**<  */
#define IOCTRL_SPIM1CR_D2_PS ( (uint32_t)1 << 20)      /**<  */
#define IOCTRL_SPIM1CR_D3_PS ( (uint32_t)1 << 21)      /**<  */
#define IOCTRL_SPIM1CR_IE (24)                 /**<  */
#define IOCTRL_SPIM1CR_SS_IE ( (uint32_t)1 << 24)      /**<  */
#define IOCTRL_SPIM1CR_SCK_IE ( (uint32_t)1 << 25)     /**<  */
#define IOCTRL_SPIM1CR_D0_IE ( (uint32_t)1 << 26)      /**<  */
#define IOCTRL_SPIM1CR_D1_IE ( (uint32_t)1 << 27)      /**<  */
#define IOCTRL_SPIM1CR_D2_IE ( (uint32_t)1 << 28)      /**<  */
#define IOCTRL_SPIM1CR_D3_IE ( (uint32_t)1 << 29)      /**<  */

/*WKUPPADCR*/
#define IOCTRL_WKUPPADCR_DS1_DS0 (0x03 << 0) /**<  */
#define IOCTRL_WKUPPADCR_DS0 ( (uint32_t)1 << 0)     /**<  */
#define IOCTRL_WKUPPADCR_DS1 ( (uint32_t)1 << 1)     /**<  */
#define IOCTRL_WKUPPADCR_SR ( (uint32_t)1 << 2)      /**<  */
#define IOCTRL_WKUPPADCR_IS ( (uint32_t)1 << 3)      /**<  */
#define IOCTRL_WKUPPADCR_WAKEUP_PS ( (uint32_t)1 << 6)      /**<  */
#define IOCTRL_WKUPPADCR_USBDET_PS ( (uint32_t)1 << 7)      /**<  */

/*EPORT2CR*/
#define IOCTRL_EPORT2CR_IE (16)              /**<  */
#define IOCTRL_EPORT2CR_DS1_DS0 (0x03 << 0) /**<  */
#define IOCTRL_EPORT2CR_DS0 ( (uint32_t)1 << 0)     /**<  */
#define IOCTRL_EPORT2CR_DS1 ( (uint32_t)1 << 1)     /**<  */
#define IOCTRL_EPORT2CR_SR ( (uint32_t)1 << 2)      /**<  */
#define IOCTRL_EPORT2CR_IS ( (uint32_t)1 << 3)      /**<  */
#define IOCTRL_EPORT2CR_IE_BIT0 ( (uint32_t)1 << 16) /**<  */
#define IOCTRL_EPORT2CR_IE_BIT1 ( (uint32_t)1 << 17) /**<  */
#define IOCTRL_EPORT2CR_IE_BIT2 ( (uint32_t)1 << 18) /**<  */
#define IOCTRL_EPORT2CR_IE_BIT3 ( (uint32_t)1 << 19) /**<  */
#define IOCTRL_EPORT2CR_IE_BIT4 ( (uint32_t)1 << 20) /**<  */
#define IOCTRL_EPORT2CR_IE_BIT5 ( (uint32_t)1 << 21) /**<  */
#define IOCTRL_EPORT2CR_IE_BIT6 ( (uint32_t)1 << 22) /**<  */
#define IOCTRL_EPORT2CR_IE_BIT7 ( (uint32_t)1 << 23) /**<  */

/*EPORT5CR*/
#define IOCTRL_EPORT5CR_IE (16)              /**<  */
#define IOCTRL_EPORT5CR_IE_MASK (0xFF << 16) /**< 0:input_dis 1:input_en */
#define IOCTRL_EPORT5CR_DS0 ( (uint32_t)1 << 0)     /**<  */
#define IOCTRL_EPORT5CR_DS1 ( (uint32_t)1 << 1)     /**<  */
#define IOCTRL_EPORT5CR_SR ( (uint32_t)1 << 2)      /**<  */
#define IOCTRL_EPORT5CR_IS ( (uint32_t)1 << 3)      /**<  */
#define IOCTRL_EPORT5CR_IE_BIT0 ( (uint32_t)1 << 16) /**<  */
#define IOCTRL_EPORT5CR_IE_BIT1 ( (uint32_t)1 << 17) /**<  */
#define IOCTRL_EPORT5CR_IE_BIT2 ( (uint32_t)1 << 18) /**<  */
#define IOCTRL_EPORT5CR_IE_BIT3 ( (uint32_t)1 << 19) /**<  */
#define IOCTRL_EPORT5CR_IE_BIT4 ( (uint32_t)1 << 20) /**<  */
#define IOCTRL_EPORT5CR_IE_BIT5 ( (uint32_t)1 << 21) /**<  */
#define IOCTRL_EPORT5CR_IE_BIT6 ( (uint32_t)1 << 22) /**<  */
#define IOCTRL_EPORT5CR_IE_BIT7 ( (uint32_t)1 << 23) /**<  */

/*EPORT6CR*/
#define IOCTRL_EPORT6CR_IE (16)              /**<  */
#define IOCTRL_EPORT6CR_IE_MASK (0xFF << 16) /**< 0:input_dis 1:input_en */
#define IOCTRL_EPORT6CR_IE_BIT0 ( (uint32_t)1 << 16) /**<  */
#define IOCTRL_EPORT6CR_IE_BIT1 ( (uint32_t)1 << 17) /**<  */
#define IOCTRL_EPORT6CR_IE_BIT2 ( (uint32_t)1 << 18) /**<  */
#define IOCTRL_EPORT6CR_IE_BIT3 ( (uint32_t)1 << 19) /**<  */
#define IOCTRL_EPORT6CR_IE_BIT4 ( (uint32_t)1 << 20) /**<  */
#define IOCTRL_EPORT6CR_IE_BIT5 ( (uint32_t)1 << 21) /**<  */
#define IOCTRL_EPORT6CR_IE_BIT6 ( (uint32_t)1 << 22) /**<  */
#define IOCTRL_EPORT6CR_IE_BIT7 ( (uint32_t)1 << 23) /**<  */

/*EPORT7CR*/
#define IOCTRL_EPORT7CR_IE (16)              /**<  */
#define IOCTRL_EPORT7CR_IE_MASK (0xFF << 16) /**< 0:input_dis 1:input_en */
#define IOCTRL_EPORT7CR_IE_BIT0 ( (uint32_t)1 << 16) /**<  */
#define IOCTRL_EPORT7CR_IE_BIT1 ( (uint32_t)1 << 17) /**<  */
#define IOCTRL_EPORT7CR_IE_BIT2 ( (uint32_t)1 << 18) /**<  */
#define IOCTRL_EPORT7CR_IE_BIT3 ( (uint32_t)1 << 19) /**<  */
#define IOCTRL_EPORT7CR_IE_BIT4 ( (uint32_t)1 << 20) /**<  */
#define IOCTRL_EPORT7CR_IE_BIT5 ( (uint32_t)1 << 21) /**<  */
#define IOCTRL_EPORT7CR_IE_BIT6 ( (uint32_t)1 << 22) /**<  */
#define IOCTRL_EPORT7CR_IE_BIT7 ( (uint32_t)1 << 23) /**<  */

/*SWAPCR2*/
#define IOCTRL_SWAPCR2_SWAP_BIT8 ( (uint32_t)1 << 8)   /**< 0:ss1 enable; 1:gint[40] enable  */
#define IOCTRL_SWAPCR2_SWAP_BIT9 ( (uint32_t)1 << 9)   /**< 0:sck1 enable; 1:gint[41] enable  */
#define IOCTRL_SWAPCR2_SWAP_BIT10 ( (uint32_t)1 << 10) /**< 0:miso1 enable; 1:gint[42] disable  */
#define IOCTRL_SWAPCR2_SWAP_BIT11 ( (uint32_t)1 << 11) /**< 0:mosi1 enable; 1:gint[43] enable  */
#define IOCTRL_SWAPCR2_SWAP_BIT12 ( (uint32_t)1 << 12) /**< 0:ss2 enable; 1:gint[44] enable  */
#define IOCTRL_SWAPCR2_SWAP_BIT13 ( (uint32_t)1 << 13) /**< 0:sck2 enable; 1:gint[45] enable  */
#define IOCTRL_SWAPCR2_SWAP_BIT14 ( (uint32_t)1 << 14) /**< 0:miso2 enable; 1:gint[46] enable */
#define IOCTRL_SWAPCR2_SWAP_BIT15 ( (uint32_t)1 << 15) /**< 0:mosi2 enable; 1:gint[47] enable */
#define IOCTRL_SWAPCR2_SWAP_BIT18 ( (uint32_t)1 << 18) /**< 0:scl enable; 1:gint[50] enable  */
#define IOCTRL_SWAPCR2_SWAP_BIT19 ( (uint32_t)1 << 19) /**< 0:sda enable; 1:gint[51] enable  */
#define IOCTRL_SWAPCR2_SWAP_BIT20 ( (uint32_t)1 << 20) /**< 0:txd enable; 1:gint[52] enable  */
#define IOCTRL_SWAPCR2_SWAP_BIT21 ( (uint32_t)1 << 21) /**< 0:rxd enable; 1:gint[53] enable  */
#define IOCTRL_SWAPCR2_SWAP_BIT22 ( (uint32_t)1 << 22) /**< 0:txd2 enable; 1:gint[54] enable  */
#define IOCTRL_SWAPCR2_SWAP_BIT23 ( (uint32_t)1 << 23) /**< 0:rxd2 enable; 1:gint[55] enable  */
#define IOCTRL_SWAPCR2_SWAP_BIT24 ( (uint32_t)1 << 24) /**< 0:txd3 enable; 1:gint[56] enable  */
#define IOCTRL_SWAPCR2_SWAP_BIT25 ( (uint32_t)1 << 25) /**< 0:rxd3 enable; 1:gint[57] enable  */
#define IOCTRL_SWAPCR2_SWAP_BIT26 ( (uint32_t)1 << 26) /**< 0:isodat2 enable; 1:gint[58] enable  */
#define IOCTRL_SWAPCR2_SWAP_BIT27 ( (uint32_t)1 << 27) /**< 0:isoclk2 enable; 1:gint[59] enable  */
#define IOCTRL_SWAPCR2_SWAP_BIT28 ( (uint32_t)1 << 28) /**< 0:isorst2 enable; 1:gint[60] enable  */
#define IOCTRL_SWAPCR2_SWAP_BIT29 ( (uint32_t)1 << 29) /**< 0:isodat1 enable; 1:gint[61] enable  */
#define IOCTRL_SWAPCR2_SWAP_BIT30 ( (uint32_t)1 << 30) /**< 0:wakeup enable; 1:gint[62] enable  */
#define IOCTRL_SWAPCR2_SWAP_BIT31 ( (uint32_t)1 << 31) /**< 0:usbdet enable; 1:gint[63] enable  */

/*SWAPCR3*/
#define IOCTRL_SWAPCR3_SWAP_BIT0 ( (uint32_t)1 << 0)   /**< 0:isoclk1 enable; 1:gint[6]enable */
#define IOCTRL_SWAPCR3_SWAP_BIT1 ( (uint32_t)1 << 1)   /**< 0:isorst1 enable; 1:gint[7] enable*/
#define IOCTRL_SWAPCR3_SWAP_BIT2 ( (uint32_t)1 << 2)   /**< 0:pwmt1_etr enable; 1:gint[14] enable */
#define IOCTRL_SWAPCR3_SWAP_BIT3 ( (uint32_t)1 << 3)   /**< 0:pwmt1_brk enable; 1:gint[15] enable */
#define IOCTRL_SWAPCR3_SWAP_BIT4 ( (uint32_t)1 << 4)   /**< 0:pwmt2_etr enable; 1:miso3 enable */
#define IOCTRL_SWAPCR3_SWAP_BIT5 ( (uint32_t)1 << 5)   /**< 0:pwmt2_brk enable; 1:mosi3 enable */
#define IOCTRL_SWAPCR3_SWAP_BIT6 ( (uint32_t)1 << 6)   /**< 0:pwmt3_etr enable; 1:ss3 enable */
#define IOCTRL_SWAPCR3_SWAP_BIT7 ( (uint32_t)1 << 7)   /**< 0:pwmt3_brk enable; 1:sck3 enable */
#define IOCTRL_SWAPCR3_SWAP_BIT8 ( (uint32_t)1 << 8)   /**< 0:pwmt1_ch0 enable; 1:gint[0] enable */
#define IOCTRL_SWAPCR3_SWAP_BIT9 ( (uint32_t)1 << 9)   /**< 0:pwmt1_ch0n enable; 1:gint[1] enable */
#define IOCTRL_SWAPCR3_SWAP_BIT10 ( (uint32_t)1 << 10) /**< 0:pwmt1_ch1 enable; 1:isoclk1 enable */
#define IOCTRL_SWAPCR3_SWAP_BIT11 ( (uint32_t)1 << 11) /**< 0:pwmt1_ch1n enable; 1:isorst1 enable */
#define IOCTRL_SWAPCR3_SWAP_BIT12 ( (uint32_t)1 << 12) /**< 0:pwmt1_ch2 enable; 1:gint[2] enable */
#define IOCTRL_SWAPCR3_SWAP_BIT13 ( (uint32_t)1 << 13) /**< 0:pwmt1_ch2n enable; 1:gint[4] enable */
#define IOCTRL_SWAPCR3_SWAP_BIT14 ( (uint32_t)1 << 14) /**< 0:pwmt1_ch3 enable; 1:gint[3] enable */
#define IOCTRL_SWAPCR3_SWAP_BIT15 ( (uint32_t)1 << 15) /**< 0:pwmt1_ch3n enable; 1:gint[5] enable */
#define IOCTRL_SWAPCR3_SWAP_BIT16 ( (uint32_t)1 << 16) /**< 0:pwmt2_ch0 enable; 1:usbdet enable */
#define IOCTRL_SWAPCR3_SWAP_BIT17 ( (uint32_t)1 << 17) /**< 0:pwmt2_ch0n enable; 1:isodat2 enable */
#define IOCTRL_SWAPCR3_SWAP_BIT18 ( (uint32_t)1 << 18) /**< 0:pwmt2_ch1 enable; 1:wakeup enable */
#define IOCTRL_SWAPCR3_SWAP_BIT19 ( (uint32_t)1 << 19) /**< 0:pwmt2_ch1n enable; 1:isoclk2 enable */
#define IOCTRL_SWAPCR3_SWAP_BIT20 ( (uint32_t)1 << 20) /**< 0:pwmt2_ch2 enable; 1:clkout enable */
#define IOCTRL_SWAPCR3_SWAP_BIT21 ( (uint32_t)1 << 21) /**< 0:pwmt2_ch2n enable; 1:isorst2 enable */
#define IOCTRL_SWAPCR3_SWAP_BIT22 ( (uint32_t)1 << 22) /**< 0:pwmt2_ch3 enable; 1:rstout enable */
#define IOCTRL_SWAPCR3_SWAP_BIT23 ( (uint32_t)1 << 23) /**< 0:pwmt2_ch3n enable; 1:isodat1 enable */

/*SWAPCR4*/
#define IOCTRL_SWAPCR4_SWAP_BIT20 ( (uint32_t)1 << 20) /**< 0:clkout enable; 1:gint[22] enable */
#define IOCTRL_SWAPCR4_SWAP_BIT21 ( (uint32_t)1 << 21) /**< 0:rstout enable; 1:gint[23] enable */

/*SWAPCR5*/
#define IOCTRL_SWAPCR5_SWAP_BIT4 ( (uint32_t)1 << 4)   /**< 0:gint[16] enable; 1:spi4[2] enable */
#define IOCTRL_SWAPCR5_SWAP_BIT5 ( (uint32_t)1 << 5)   /**< 0:gint[17] enable; 1:spi4[3] enable */
#define IOCTRL_SWAPCR5_SWAP_BIT6 ( (uint32_t)1 << 6)   /**< 0:gint[18] enable; 1:spi4[0] enable */
#define IOCTRL_SWAPCR5_SWAP_BIT7 ( (uint32_t)1 << 7)   /**< 0:gint[19] enable; 1:spi4[1] enable */
#define IOCTRL_SWAPCR5_SWAP_BIT8 ( (uint32_t)1 << 8)   /**< 0:gint[20] enable; 1:spi4_sck enable */
#define IOCTRL_SWAPCR5_SWAP_BIT9 ( (uint32_t)1 << 9)   /**< 0:gint[21] enable; 1:spi4_ss enable */

/*PWMTCR*/
#define IOCTRL_PWMTCR_PWMT1_ETR_PUE ( (uint32_t)1 << 0) /**<  */
#define IOCTRL_PWMTCR_PWMT1_BRK_PUE ( (uint32_t)1 << 1) /**<  */
#define IOCTRL_PWMTCR_PWMT2_ETR_PUE ( (uint32_t)1 << 2) /**<  */
#define IOCTRL_PWMTCR_PWMT2_BRK_PUE ( (uint32_t)1 << 3) /**<  */

/*SPI1CR*/
#define IOCTRL_SPI1CR_D_DS1_DS0 (0x03 << 0)   /**< 00=2mA 01=8mA 10=4mA 11=12mA */
#define IOCTRL_SPI1CR_D_DS0 ( (uint32_t)1 << 0)       /**<  */
#define IOCTRL_SPI1CR_D_DS1 ( (uint32_t)1 << 1)       /**<  */
#define IOCTRL_SPI1CR_D_SR ( (uint32_t)1 << 2)        /**<  */
#define IOCTRL_SPI1CR_D_IS ( (uint32_t)1 << 3)        /**<  */
#define IOCTRL_SPI1CR_SCK_DS1_DS0 (0x03 << 8) /**<  */
#define IOCTRL_SPI1CR_SCK_DS0 ( (uint32_t)1 << 8)     /**<  */
#define IOCTRL_SPI1CR_SCK_DS1 ( (uint32_t)1 << 9)     /**<  */
#define IOCTRL_SPI1CR_SCK_SR ( (uint32_t)1 << 10)     /**<  */
#define IOCTRL_SPI1CR_SCK_IS ( (uint32_t)1 << 11)     /**<  */
#define IOCTRL_SPI1CR_SS_DS1_DS0 (0x03 << 12) /**<  */
#define IOCTRL_SPI1CR_SS_DS0 ( (uint32_t)1 << 12)     /**<  */
#define IOCTRL_SPI1CR_SS_DS1 ( (uint32_t)1 << 13)     /**<  */
#define IOCTRL_SPI1CR_SS_SR ( (uint32_t)1 << 14)      /**<  */
#define IOCTRL_SPI1CR_SS_IS ( (uint32_t)1 << 15)      /**<  */

/*SPI2CR*/
#define IOCTRL_SPI2CR_D_DS1_DS0 (0x03 << 0)   /**< 00=2mA 01=8mA 10=4mA 11=12mA */
#define IOCTRL_SPI2CR_D_DS0 ( (uint32_t)1 << 0)       /**<  */
#define IOCTRL_SPI2CR_D_DS1 ( (uint32_t)1 << 1)       /**<  */
#define IOCTRL_SPI2CR_D_SR ( (uint32_t)1 << 2)        /**<  */
#define IOCTRL_SPI2CR_D_IS ( (uint32_t)1 << 3)        /**<  */
#define IOCTRL_SPI2CR_SCK_DS1_DS0 (0x03 << 8) /**<  */
#define IOCTRL_SPI2CR_SCK_DS0 ( (uint32_t)1 << 8)     /**<  */
#define IOCTRL_SPI2CR_SCK_DS1 ( (uint32_t)1 << 9)     /**<  */
#define IOCTRL_SPI2CR_SCK_SR ( (uint32_t)1 << 10)     /**<  */
#define IOCTRL_SPI2CR_SCK_IS ( (uint32_t)1 << 11)     /**<  */
#define IOCTRL_SPI2CR_SS_DS1_DS0 (0x03 << 12) /**<  */
#define IOCTRL_SPI2CR_SS_DS0 ( (uint32_t)1 << 12)     /**<  */
#define IOCTRL_SPI2CR_SS_DS1 ( (uint32_t)1 << 13)     /**<  */
#define IOCTRL_SPI2CR_SS_SR ( (uint32_t)1 << 14)      /**<  */
#define IOCTRL_SPI2CR_SS_IS ( (uint32_t)1 << 15)      /**<  */

/*SPI3CR*/
#define IOCTRL_SPI3CR_D_DS1_DS0 (0x03 << 0)   /**< 00=2mA 01=8mA 10=4mA 11=12mA */
#define IOCTRL_SPI3CR_D_DS0 ( (uint32_t)1 << 0)       /**<  */
#define IOCTRL_SPI3CR_D_DS1 ( (uint32_t)1 << 1)       /**<  */
#define IOCTRL_SPI3CR_D_SR ( (uint32_t)1 << 2)        /**<  */
#define IOCTRL_SPI3CR_D_IS ( (uint32_t)1 << 3)        /**<  */
#define IOCTRL_SPI3CR_SCK_DS1_DS0 (0x03 << 8) /**<  */
#define IOCTRL_SPI3CR_SCK_DS0 ( (uint32_t)1 << 8)     /**<  */
#define IOCTRL_SPI3CR_SCK_DS1 ( (uint32_t)1 << 9)     /**<  */
#define IOCTRL_SPI3CR_SCK_SR ( (uint32_t)1 << 10)     /**<  */
#define IOCTRL_SPI3CR_SCK_IS ( (uint32_t)1 << 11)     /**<  */
#define IOCTRL_SPI3CR_SS_DS1_DS0 (0x03 << 12) /**<  */
#define IOCTRL_SPI3CR_SS_DS0 ( (uint32_t)1 << 12)     /**<  */
#define IOCTRL_SPI3CR_SS_DS1 ( (uint32_t)1 << 13)     /**<  */
#define IOCTRL_SPI3CR_SS_SR ( (uint32_t)1 << 14)      /**<  */
#define IOCTRL_SPI3CR_SS_IS ( (uint32_t)1 << 15)      /**<  */

/*WDTCR*/
#define IOCTRL_WDTCR_EN ( (uint32_t)1 << 15)          

/*SWAPCR6*/
#define IOCTRL_SWAPCR6_SWAP_BIT0 ( (uint32_t)1 << 0)   /**< 0:gint[15] enable; 1:pwm4 enable */
#define IOCTRL_SWAPCR6_SWAP_BIT1 ( (uint32_t)1 << 1)   /**< 0:ss2 enable; 1:SS_SPI4 enable */
#define IOCTRL_SWAPCR6_SWAP_BIT2 ( (uint32_t)1 << 2)   /**< 0:sck2 enable; 1:SCK_SPI4 enable */
#define IOCTRL_SWAPCR6_SWAP_BIT3 ( (uint32_t)1 << 3)   /**< 0:mosi2 enable; 1:SPI4[0] enable */
#define IOCTRL_SWAPCR6_SWAP_BIT4 ( (uint32_t)1 << 4)   /**< 0:miso2 enable; 1:SPI4[1] enable */
#define IOCTRL_SWAPCR6_SWAP_BIT5 ( (uint32_t)1 << 5)   /**< 0:txd enable; 1:SPI4[2] enable */
#define IOCTRL_SWAPCR6_SWAP_BIT6 ( (uint32_t)1 << 6)   /**< 0:rxd enable; 1:SPI4[3] enable */
#define IOCTRL_SWAPCR6_SWAP_BIT7 ( (uint32_t)1 << 7)   /**< 0:wakeup2 enable; 1:gint enable */

#endif /* end __IO_CONTROL__ */

#define __PIT__
#ifdef __PIT__
/*****************  Bit definition for PIT_PCSR/PIT32_PCSR register  *****************/
#define PIT_PCSR_EN (1 << 0) /**< =1,则PIT使能 */
#define PIT_PCSR_RLD (1 << 1)
#define PIT_PCSR_PIF (1 << 2) /**< =1,则PIT计数达到了0,并且产生了中断信号 */
#define PIT_PCSR_PIE (1 << 3) /**< =1,则PIT中断请求使能 */
#define PIT_PCSR_OVW (1 << 4)
#define PIT_PCSR_PDBG (1 << 5)
#define PIT_PCSR_PDOZE (1 << 6)
#define PIT_PCSR_PRESCALER_1 (0x00 << 8)     /**< PIT模块分频数值:1分频    */
#define PIT_PCSR_PRESCALER_2 ( (uint32_t)1 << 8)     /**< PIT模块分频数值:2分频    */
#define PIT_PCSR_PRESCALER_4 (0x02 << 8)     /**< PIT模块分频数值:4分频    */
#define PIT_PCSR_PRESCALER_8 (0x03 << 8)     /**< PIT模块分频数值:8分频    */
#define PIT_PCSR_PRESCALER_16 (0x04 << 8)    /**< PIT模块分频数值:16分频   */
#define PIT_PCSR_PRESCALER_32 (0x05 << 8)    /**< PIT模块分频数值:32分频   */
#define PIT_PCSR_PRESCALER_64 (0x06 << 8)    /**< PIT模块分频数值:64分频   */
#define PIT_PCSR_PRESCALER_128 (0x07 << 8)   /**< PIT模块分频数值:128分频  */
#define PIT_PCSR_PRESCALER_256 (0x08 << 8)   /**< PIT模块分频数值:256分频  */
#define PIT_PCSR_PRESCALER_512 (0x09 << 8)   /**< PIT模块分频数值:512分频  */
#define PIT_PCSR_PRESCALER_1024 (0x0a << 8)  /**< PIT模块分频数值:1024分频 */
#define PIT_PCSR_PRESCALER_2048 (0x0b << 8)  /**< PIT模块分频数值:分频2048 */
#define PIT_PCSR_PRESCALER_4096 (0x0c << 8)  /**< PIT模块分频数值:分频4096 */
#define PIT_PCSR_PRESCALER_8192 (0x0d << 8)  /**< PIT模块分频数值:分频8192 */
#define PIT_PCSR_PRESCALER_16384 (0x0e << 8) /**< PIT模块分频数值:分频16384 */
#define PIT_PCSR_PRESCALER_32968 (0x0f << 8) /**< PIT模块分频数值:分频32768 */

#endif /* end __PIT__ */


#define __PWM__
#ifdef __PWM__
/*****************  Bit definition for PWM register  *****************/
#define PWM_PDZR1_DZ3_SHIFT               24     
#define PWM_PDZR1_DZ2_SHIFT               16
#define PWM_PDZR1_DZ1_SHIFT               8    
#define PWM_PDZR1_DZ0_SHIFT               0  
#define PWM_PPR_CP3_SHIFT                 24     
#define PWM_PPR_CP2_SHIFT                 16
#define PWM_PPR_CP1_SHIFT                 8     
#define PWM_PPR_CP0_SHIFT                 0     

#define PWM_PCSR_CSR7_SHIFT 28
#define PWM_PCSR_CSR6_SHIFT 24
#define PWM_PCSR_CSR5_SHIFT 20
#define PWM_PCSR_CSR4_SHIFT 16
#define PWM_PCSR_CSR3_SHIFT 12
#define PWM_PCSR_CSR2_SHIFT 8
#define PWM_PCSR_CSR1_SHIFT 4
#define PWM_PCSR_CSR0_SHIFT 0

#define PWM_PCR_CH0EN (1 << 0)
#define PWM_PCR_CH0INV (1 << 2)
#define PWM_PCR_CH0MOD (1 << 3)
#define PWM_PCR_DZ0EN (1 << 4)
#define PWM_PCR_DZ1EN (1 << 5)
#define PWM_PCR_CH1EN (1 << 8)
#define PWM_PCR_CH1INV (1 << 10)
#define PWM_PCR_CH1MOD (1 << 11)
#define PWM_PCR_CH2EN (1 << 16)
#define PWM_PCR_CH2INV (1 << 18)
#define PWM_PCR_CH2MOD (1 << 19)
#define PWM_PCR_CH3EN (1 << 24)
#define PWM_PCR_CH3INV (1 << 26)
#define PWM_PCR_CH3MOD (1 << 27)
#define PWM_PCR_CH4EN (1 << 1)
#define PWM_PCR_CH5EN (1 << 9)
#define PWM_PCR_CH6EN (1 << 17)
#define PWM_PCR_CH7EN (1 << 25)

#define PWM_PCR1_CH4INV (1 << 2)
#define PWM_PCR1_CH4MOD (1 << 3)
#define PWM_PCR1_CH5INV (1 << 10)
#define PWM_PCR1_CH5MOD (1 << 11)
#define PWM_PCR1_CH6INV (1 << 18)
#define PWM_PCR1_CH6MOD (1 << 19)
#define PWM_PCR1_CH7INV (1 << 26)
#define PWM_PCR1_CH7MOD (1 << 27)
#define PWM_PCR1_DZ2EN (1 << 4)
#define PWM_PCR1_DZ3EN (1 << 5)

#define PWM_PIER_CH0INT_EN (1 << 0)
#define PWM_PIER_CH1INT_EN (1 << 1)
#define PWM_PIER_CH2INT_EN (1 << 2)
#define PWM_PIER_CH3INT_EN (1 << 3)
#define PWM_PIER_CH4INT_EN (1 << 4)
#define PWM_PIER_CH5INT_EN (1 << 5)
#define PWM_PIER_CH6INT_EN (1 << 6)
#define PWM_PIER_CH7INT_EN (1 << 7)

#define PWM_PIFR_CH0INT (1 << 0)
#define PWM_PIFR_CH1INT (1 << 1)
#define PWM_PIFR_CH2INT (1 << 2)
#define PWM_PIFR_CH3INT (1 << 3)
#define PWM_PIFR_CH4INT (1 << 4)
#define PWM_PIFR_CH5INT (1 << 5)
#define PWM_PIFR_CH6INT (1 << 6)
#define PWM_PIFR_CH7INT (1 << 7)

#define PWM_PCCR0_CH0_INV (1 << 0)
#define PWM_PCCR0_CH0_RLINT (1 << 1)
#define PWM_PCCR0_CH0_FLINT (1 << 2)
#define PWM_PCCR0_CH0_CAPEN (1 << 3)
#define PWM_PCCR0_CH0_CAPIF (1 << 4)
#define PWM_PCCR0_CH0_CRLRD (1 << 6)
#define PWM_PCCR0_CH0_CFLRD (1 << 7)
#define PWM_PCCR0_CH1_INV (1 << 16)
#define PWM_PCCR0_CH1_RLINT (1 << 17)
#define PWM_PCCR0_CH1_FLINT (1 << 18)
#define PWM_PCCR0_CH1_CAPEN (1 << 19)
#define PWM_PCCR0_CH1_CAPIF (1 << 20)
#define PWM_PCCR0_CH1_CRLRD (1 << 22)
#define PWM_PCCR0_CH1_CFLRD (1 << 23)

#define PWM_PCCR1_CH2_INV (1 << 0)
#define PWM_PCCR1_CH2_RLINT (1 << 1)
#define PWM_PCCR1_CH2_FLINT (1 << 2)
#define PWM_PCCR1_CH2_CAPEN (1 << 3)
#define PWM_PCCR1_CH2_CAPIF (1 << 4)
#define PWM_PCCR1_CH2_CRLRD (1 << 6)
#define PWM_PCCR1_CH2_CFLRD (1 << 7)
#define PWM_PCCR1_CH3_INV (1 << 16)
#define PWM_PCCR1_CH3_RLINT (1 << 17)
#define PWM_PCCR1_CH3_FLINT (1 << 18)
#define PWM_PCCR1_CH3_CAPEN (1 << 19)
#define PWM_PCCR1_CH3_CAPIF (1 << 20)
#define PWM_PCCR1_CH3_CRLRD (1 << 22)
#define PWM_PCCR1_CH3_CFLRD (1 << 23)

#define PWM_PCCR2_CH4_INV   (1 << 0)
#define PWM_PCCR2_CH4_RLINT (1 << 1)
#define PWM_PCCR2_CH4_FLINT (1 << 2)
#define PWM_PCCR2_CH4_CAPEN (1 << 3)
#define PWM_PCCR2_CH4_CAPIF (1 << 4)
#define PWM_PCCR2_CH4_CRLRD (1 << 6)
#define PWM_PCCR2_CH4_CFLRD (1 << 7)
#define PWM_PCCR2_CH5_INV   (1 << 16)
#define PWM_PCCR2_CH5_RLINT (1 << 17)
#define PWM_PCCR2_CH5_FLINT (1 << 18)
#define PWM_PCCR2_CH5_CAPEN (1 << 19)
#define PWM_PCCR2_CH5_CAPIF (1 << 20)
#define PWM_PCCR2_CH5_CRLRD (1 << 22)
#define PWM_PCCR2_CH5_CFLRD (1 << 23)

#define PWM_PCCR3_CH6_INV   (1 << 0)
#define PWM_PCCR3_CH6_RLINT (1 << 1)
#define PWM_PCCR3_CH6_FLINT (1 << 2)
#define PWM_PCCR3_CH6_CAPEN (1 << 3)
#define PWM_PCCR3_CH6_CAPIF (1 << 4)
#define PWM_PCCR3_CH6_CRLRD (1 << 6)
#define PWM_PCCR3_CH6_CFLRD (1 << 7)
#define PWM_PCCR3_CH7_INV   (1 << 16)
#define PWM_PCCR3_CH7_RLINT (1 << 17)
#define PWM_PCCR3_CH7_FLINT (1 << 18)
#define PWM_PCCR3_CH7_CAPEN (1 << 19)
#define PWM_PCCR3_CH7_CAPIF (1 << 20)
#define PWM_PCCR3_CH7_CRLRD (1 << 22)
#define PWM_PCCR3_CH7_CFLRD (1 << 23)

#define PWM_PPCR_CH0_BITSET (1 << 0)
#define PWM_PPCR_CH1_BITSET (1 << 1)
#define PWM_PPCR_CH2_BITSET (1 << 2)
#define PWM_PPCR_CH3_BITSET (1 << 3)
#define PWM_PPCR_CH4_BITSET (1 << 4)
#define PWM_PPCR_CH5_BITSET (1 << 5)
#define PWM_PPCR_CH6_BITSET (1 << 6)
#define PWM_PPCR_CH7_BITSET (1 << 7)
#define PWM_PPCR_CH0_PULLUP (1 << 8)
#define PWM_PPCR_CH1_PULLUP (1 << 9)
#define PWM_PPCR_CH2_PULLUP (1 << 10)
#define PWM_PPCR_CH3_PULLUP (1 << 11)
#define PWM_PPCR_CH4_PULLUP (1 << 12)
#define PWM_PPCR_CH5_PULLUP (1 << 13)
#define PWM_PPCR_CH6_PULLUP (1 << 14)
#define PWM_PPCR_CH7_PULLUP (1 << 15)
#define PWM_PPCR_CH0_OUTPUT (1 << 16)
#define PWM_PPCR_CH1_OUTPUT (1 << 17)
#define PWM_PPCR_CH2_OUTPUT (1 << 18)
#define PWM_PPCR_CH3_OUTPUT (1 << 19)
#define PWM_PPCR_CH4_OUTPUT (1 << 20)
#define PWM_PPCR_CH5_OUTPUT (1 << 21)
#define PWM_PPCR_CH6_OUTPUT (1 << 22)
#define PWM_PPCR_CH7_OUTPUT (1 << 23)

#define PWM_PFPM_CH0_ENABLE (1 << 0)
#define PWM_PFPM_CH1_ENABLE (1 << 1)
#define PWM_PFPM_CH2_ENABLE (1 << 2)
#define PWM_PFPM_CH3_ENABLE (1 << 3)
#define PWM_PFPM_CH4_ENABLE (1 << 4)
#define PWM_PFPM_CH5_ENABLE (1 << 5)
#define PWM_PFPM_CH6_ENABLE (1 << 6)
#define PWM_PFPM_CH7_ENABLE (1 << 7)
#define PWM_PFPM_PDER       (1 << 31)

#endif /* end __PWM__ */
#define __RESET__
#ifdef __RESET__
/*** RESET **********************************************/
/*** RCR ************/
#define RESET_RCR_SOFTRST (((uint32_t)1U << 31))

#define RESET_RSR_POR   ((uint32_t)1U << 3)
#define RESET_RSR_QDR   ((uint32_t)1U << 4)
#define RESET_RSR_SOFT  ((uint32_t)1U << 5)
#define RESET_RSR_TCR   ((uint32_t)1U << 7)

#endif /* end RESET */

#define __SECDET__
#ifdef __SECDET__
/*** SECURE DETECT **********************************************/
/*** TS1CR ************/
#define SECDET_TS1CR_HT_HYS (((uint32_t)1U << 9))
#define SECDET_TS1CR_LT_HYS (((uint32_t)1U << 10))
#define SECDET_TS1CR_TS_EN (((uint32_t)1U << 11))
#define SECDET_TS1CR_BG_EN (((uint32_t)1U << 12))
#define SECDET_TS1CR_TS_HTEMP_REN (((uint32_t)1U << 27))
#define SECDET_TS1CR_TS_HTEMP_IEN (((uint32_t)1U << 28))
#define SECDET_TS1CR_TS_TEMP_ST_SEL (((uint32_t)1U << 29))
#define SECDET_TS1CR_TS_LTEMP_REN (((uint32_t)1U << 30))
#define SECDET_TS1CR_TS_LTEMP_IEN (((uint32_t)1U << 31))

/*** TS1SR ************/
#define SECDET_TS1SR_TS_LTEMP_ST (((uint32_t)1U << 0))
#define SECDET_TS1SR_TS_HTEMP_ST (((uint32_t)1U << 1))
#define SECDET_TS1SR_TS_LTEMP_ST_LAT (((uint32_t)1U << 2))
#define SECDET_TS1SR_TS_HTEMP_ST_LAT (((uint32_t)1U << 3))

/*** OBTCR ************/
#define SECDET_OBTCR_BIST_EN (((uint32_t)1U << 8))
#define SECDET_OBTCR_BIST_IRC_EN (((uint32_t)1U << 10))
#define SECDET_OBTCR_BIST_START (((uint32_t)1U << 15))

/*** OBTCR ************/
#define SECDET_LFTR_BIST_TRACE_LOOP (((uint32_t)1U << 16))


#endif /* end __SECDET__ */

#define __SPI__
#ifdef __SPI__
/*** SPI **********************************************/
/*SPIFR*/
#define SPI_FRAME_FORMAT_TI ((uint8_t)(1 << 4))                      /*!< TI frame format*/
#define SPI_FRAME_FORMAT_FREESCALE ((uint8_t)(~SPI_FRAME_FORMAT_TI)) /*!< freescale frame format*/
#define SPI_LOOP_BACK_MODE ((uint8_t)(1 << 5))                       /*!< loop back mode*/
#define SPI_LOOP_NORMAL_MODE ((uint8_t)(~SPI_LOOP_BACK_MODE))        /*!< normal mode*/
#define SPI_EN_GUARD_TIME ((uint8_t)(1 << 6))                        /*!< guard time is enable*/
#define SPI_DIS_GUARD_TIME ((uint8_t)(~SPI_EN_GUARD_TIME))           /*!< guard time is disable*/
#define SPI_EN_CONT_CS ((uint8_t)(1 << 7))                           /*!< keep peripheral chip select signal low between transfer until EOTF is set*/
#define SPI_DIS_CONT_CS ((uint8_t)(~SPI_EN_CONT_CS))                 /*!< return peripheral chip select singnal to high between transfers*/
#define SPI_FRAME_SIZE_MASK ((uint8_t)(0xF0))                        /*!< SPI frame size mask*/
#define SPI_FRAME_SIZE_SHIFT_MASK ((uint8_t)(0))                     /*!< SPI frame size shift*/

/*CR1*/
#define SPI_FIRSTBIT_LSB ((uint8_t)(1 << 0))             /*!< SPI LSB data to be transmitted first enable*/
#define SPI_FIRSTBIT_MSB ((uint8_t)(0xFE))               /*!< SPI MSB data to be transmitted first enable */
#define SPI_EN_SSOE ((uint8_t)(1 << 1))                  /*!< SPI Select the output pin for the input or slave enable*/
#define SPI_DIS_SSOE ((uint8_t)(0xFD))                   /*!< SPI Select the output pin for the input or slave disable*/
#define SPI_CPHA_1EDGE ((uint8_t)(0xFB))                 /*!< SPI 1/2 cycle of the first edge of the SCK after the transfer begins*/
#define SPI_CPHA_2EDGE ((uint8_t)(1 << 2))               /*!< SPI The first edge of the SCK after the transfer begins is the shift edge*/
#define SPI_CPOL_HIGH ((uint8_t)(1 << 3))                /*!< SPI high-state active clock; SCK is low when idle*/
#define SPI_CPOL_LOW ((uint8_t)(0xF7))                   /*!< SPI low-state active clock; SCK is low when idle*/
#define SPI_MASTER ((uint8_t)(1 << 4))                   /*!< SPI master mode*/
#define SPI_SLAVE ((uint8_t)(0xEF))                      /*!< SPI slave mode*/
#define SPI_WIRED_OR_MODE_OPEN_DRAIN ((uint8_t)(1 << 5)) /*!< SPI write or mode open-drain*/
#define SPI_WIRED_OR_MODE_CMOS ((uint8_t)(0xDF))         /*!< SPI cmos mode */
#define SPI_EN_SSOE ((uint8_t)(1 << 1))                  /*!< SPI ss enable*/
#define SPI_EN ((uint8_t)(1 << 6))                       /*!< SPI module enable*/
#define SPI_DIS ((uint8_t)(0xBF))                        /*!< SPI module disable*/
#define SPI_EN_IT ((uint8_t)(1 << 7))                    /*!< SPI interrupt enable */
#define SPI_DIS_IT ((uint8_t)(~SPI_EN_IT))               /*!< SPI interrupt disable*/

/*SPICR2*/
#define SPI_SPC0_BIDIR_MODE ((uint8_t)(1 << 0))          /**< SPI Serial pin control bits, Bidirectional pin mode*/
#define SPI_SPC0_NORMAL_MODE ((uint8_t)(0xFE))           /**< SPI Serial pin control bits,, Normal pin mode*/
#define SPI_DOZE_INACTIVE_MODE ((uint8_t)(1 << 1))       /**< SPI stop in sleep mode*/
#define SPI_DOZE_ACTIVE_MODE ((uint8_t)(0xFD))           /**< SPI running in sleep mode*/
#define SPI_GUARD_TIME_MASK ((uint8_t)(0x03))            /**< SPI guard time bit*/
#define SPI_GUARD_TIME_SHIFT_MASK ((uint8_t)(2))         /**< SPI guard time shift mask*/

/*SPITXFTOCTR TX FIFO timeout counter register*/
#define SPI_EN_TX_FIFO_TINEOUT ((uint8_t)(1 << 6))                         /*!< SPI TX FIFO timeout funtion enable   */
#define SPI_DIS_TX_FIFO_TIMEOUT ((uint8_t)(~SPI_EN_TX_FIFO_TINEOUT))       /*!< SPI TX FIFO timeout funtion disable  */
#define SPI_EN_TX_FIFO_TINEOUT_IT ((uint8_t)(1 << 7))                      /*!< SPI TX FIFO timeout interrupt enable */
#define SPI_DIS_TX_FIFO_TIMEOUT_IT ((uint8_t)(~SPI_EN_TX_FIFO_TINEOUT_IT)) /*!< SPI TX FIFO timeout interrupt disable*/
#define SPI_TX_FIFO_TIMEOUT_CNT_MASK ((uint8_t)(0xC0))

/*SPITXFTOCTR RX FIFO timeout counter register*/
#define SPI_EN_RX_FIFO_TINEOUT ((uint8_t)(1 << 6))                         /*!< SPI RX FIFO timeout funtion enable   */
#define SPI_DIS_RX_FIFO_TIMEOUT ((uint8_t)(~SPI_EN_RX_FIFO_TINEOUT))       /*!< SPI RX FIFO timeout funtion disable  */
#define SPI_EN_RX_FIFO_TINEOUT_IT ((uint8_t)(1 << 7))                      /*!< SPI RX FIFO timeout interrupt enable */
#define SPI_DIS_RX_FIFO_TIMEOUT_IT ((uint8_t)(~SPI_EN_RX_FIFO_TINEOUT_IT)) /*!< SPI RX FIFO timeout interrupt disable*/
#define SPI_RX_FIFO_TIMEOUT_CNT_MASK ((uint8_t)(0xC0))

/*SPI TX FIFO control register*/
#define SPI_EN_TX_FIFO_SERVICE_THRESHOLD_IT ((uint8_t)(1 << 4)) /*!< SPI TX FIFO Service threshold interrupt enable setting*/
#define SPI_EN_TX_FIFO_UNDERFLOW_IT ((uint8_t)(1 << 5))         /*!< SPI TX FIFO under-overflow interrupt enable setting*/
#define SPI_EN_TX_FIFO_OVERFLOW_IT ((uint8_t)(1 << 6))          /*!< SPI TX FIFO overflow interrupt enable setting*/
#define SPI_TX_FIFO_CLEAR ((uint8_t)(1 << 7))                   /*!< SPI TX FIFO clear enable setting*/
#define SPI_TX_FIFO_SERVICE_TRHESHOLD_MASK ((uint8_t)(0xF0))    /*!< SPI TX FIFO Service threshold*/
#define SPI_TX_FIFO_SERVICE_TRHESHOLD_SHIFT_MASK ((uint8_t)(0)) /*!< SPI TX FIFO Service threshold shift*/

/*SPI RX FIFO control register*/
#define SPI_EN_RX_FIFO_SERVICE_THRESHOLD_IT ((uint8_t)(1 << 4))
#define SPI_EN_RX_FIFO_UNDERFLOW_IT ((uint8_t)(1 << 5))         /*!< SPI RX FIFO service trheshold interrupt setting*/
#define SPI_EN_RX_FIFO_OVERFLOW_IT ((uint8_t)(1 << 6))          /*!< SPI RX FIFO under-overflow interrupt setting*/
#define SPI_RX_FIFO_CLEAR ((uint8_t)(1 << 7)) /**< */           /*!< SPI RX FIFO overflow interrupt setting*/
#define SPI_RX_FIFO_SERVICE_TRHESHOLD_MASK ((uint8_t)(0xF0))    /*!< SPI RX FIFO service trheshold mask*/
#define SPI_RX_FIFO_SERVICE_TRHESHOLD_SHIFT_MASK ((uint8_t)(0)) /*!< SPI RX FIFO service trheshold shift mask*/

/*SPIPURD Pullup and reduced driver register*/
#define SPI_EN_PULLUP_DEVICE ((uint8_t)(1 << 0))                                 /**< SPI pins pullup setting*/
#define SPI_EN_DOUBLE_TX_DATA_MODE ((uint8_t)(1 << 1))                           /**< */
#define SPI_DIS_DOUBLE_TX_DATA_MODE_DIS ((uint8_t)(~SPI_EN_DOUBLE_TX_DATA_MODE)) /**< */
#define SPI_EN_MISO_MOSI_SWITCH ((uint8_t)(1 << 2))                              /**< */
#define SPI_DIS_MISO_MOSI_SWITCH ((uint8_t)(~SPI_EN_MISO_MOSI_SWITCH))           /**< */
#define SPI_EN_HIGH_SPEED ((uint8_t)(1 << 7))                                    /**< SPI */
#define SPI_DIS_HIGH_SPEED ((uint8_t)(0x7F))                                     /**< SPI */
#define SPI_MASTER_SAMPLE_POINT_DELAY_MASK ((uint8_t)(0xF3))                     /**< */
#define SPI_MASTER_SAMPLE_POINT_DELAY_SHIFT_MASK ((uint8_t)(2))                  /**< */
#define SPI_REDUCE_CAP ((uint8_t)(1 << 4))                                       /**< SPI */
#define SPI_FULL_DRIVER ((uint8_t)(0xEF))                                        /**< SPI */
#define SPI_EN_PULLDOWN_DEVICE ((uint8_t)(1 << 1))                               /**< SPI */
#define SPI_DIS_PULLDOWN_DEVICE ((uint8_t)(0xFD))                                /**< SPI */
#define SPI_DIS_DIS_PULLUP_DEVICE ((uint8_t)(0xFE))                              /**< SPI */
#define SPI_PPS_SHIFT_MASK (4)
#define SPI_DDRSP_SHIFT_MASK (0)

/*IRSP interrupt register of SS*/
#define SPI_SS_PIN_ASSIGNMENT_SEL_MASK ((uint8_t)(0x03))       /**< */
#define SPI_SS_PIN_ASSIGNMENT_SEL_SHIFT_MASK ((uint8_t)(0x03)) /**< */
#define SPI_SS_PIN_DATA_BIT ((uint8_t)(1 << 2))                /**< */
#define SPI_SS_LEVEL_HIGH ((uint8_t)(1 << 3))                  /**< */
#define SPI_SS_LEVEL_LOW ((uint8_t)(~SPI_SS_LEVEL_HIGH))       /**< */
#define SPI_SS_PIN_FLAG ((uint8_t)(1 << 4))                    /**< */
#define SPI_EN_SS_IT ((uint8_t)(1 << 7))                       /**< */
#define SPI_DIS_SS_IT ((uint8_t)(~SPI_EN_SS_IT))               /**< */

/*TX FIFO status register*/
#define SPI_TX_FIFO_NEXT_POINTER_MASK ((uint8_t)(0x0F))       /**< */
#define SPI_TX_FIFO_NEXT_POINTER_SHIFT_MASK ((uint8_t)(0x0F)) /**< */
#define SPI_TX_FIFO_COUNTER_MASK ((uint8_t)(0xF0))            /**< */
#define SPI_TX_FIFO_COUNTER_SHIFT_MASK ((uint8_t)(0x00))      /**< */

/*RX FIFO status register*/
#define SPI_RX_FIFO_NEXT_POINTER_MASK ((uint8_t)(0x0F))       /**< */
#define SPI_RX_FIFO_NEXT_POINTER_SHIFT_MASK ((uint8_t)(0x0F)) /**< */
#define SPI_RX_FIFO_COUNTER_MASK ((uint8_t)(0xF0))            /**< */
#define SPI_RX_FIFO_COUNTER_SHIFT_MASK ((uint8_t)(0x00))      /**< */

/*SPI status register*/
#define SPI_FLAG_RX_FIFO_EMPTY ((uint8_t)(1 << 0))      /*!< SPI RX FIFO empty flag*/
#define SPI_FLAG_RX_FIFO_FULL ((uint8_t)(1 << 1))       /*!< SPI RX FIFO full flag*/
#define SPI_FLAG_TX_FIFO_EMPTY ((uint8_t)(1 << 2))      /*!< SPI TX FIFO empty flag */
#define SPI_FLAG_TX_FIFO_FULL ((uint8_t)(1 << 3))       /*!< SPI TX FIFO full flag*/
#define SPI_FLAG_MODE_FAULT ((uint8_t)(1 << 4))         /*!< SPI Mode error flag*/
#define SPI_FLAG_TRANSMISSION_END ((uint8_t)(1 << 5))   /*!< SPI End of Transmission flag */
#define SPI_FLAG_FRAME_LOST ((uint8_t)(1 << 6))         /*!< SPI Frame loss flag*/
#define SPI_FLAG_FINISH ((uint8_t)(1 << 7))             /*!< SPI single transfer completion flag*/
#define SPI_FLAG_RX_FIFO_SERVICE ((uint8_t)(1 << 8))    /*!< SPI RX FIFO data threshold indicator */
#define SPI_FLAG_RX_FIFO_UNDEFLOW ((uint8_t)(1 << 9))   /*!< SPI RX FIFO under-overflow flag*/
#define SPI_FLAG_RX_FIFO_OVERFLOW ((uint8_t)(1 << 10))  /*!< SPI RX FIFO overflow flag*/
#define SPI_FLAG_RX_FIFO_TIMEOUT ((uint8_t)(1 << 11))   /*!< SPI RX FIFO timeout flag*/
#define SPI_FLAG_TX_FIFO_SERVICE ((uint8_t)(1 << 12))   /*!< SPI TX FIFO data threshold indicator */
#define SPI_FLAG_TX_FIFO_UNDERFLOW ((uint8_t)(1 << 13)) /*!< SPI TX FIFO under-overflow flag*/
#define SPI_FLAG_TX_FIFO_OVERFLOW ((uint8_t)(1 << 14))  /*!< SPI TX FIFO overflow flag*/
#define SPI_FLAG_TX_FIFO_TIMEOUT ((uint8_t)(1 << 15))   /*!< SPI TX FIFO timeout flag*/

/*interrupt control register*/
#define SPI_EN_MODE_FAULT_IT ((uint8_t)(1 << 4))                 /**< */
#define SPI_DIS_MODE_FAULT_IT ((uint8_t)(~SPI_EN_MODE_FAULT_IT)) /**< */

// #define SPI_EN_FRAME_LOST_IT ((uint8_t)(1 << 5))                 /**< */
#define SPI_EN_FRAME_LOST_IT ((uint8_t)(1 << 6))                 /**< */
#define SPI_DIS_FRAME_LOST_IT ((uint8_t)(~SPI_EN_FRAME_LOST_IT)) /**< */

/*SPI DMA threshold register*/
#define SPI_TX_DMA_THRESHOLD_MASK ((uint8_t)(0x0F))       /**< */
#define SPI_TX_DMA_THRESHOLD_SHIFT_MASK ((uint8_t)(0x04)) /**< */
#define SPI_RX_DMA_THRESHOLD_MASK ((uint8_t)(0xF0))       /**< */
#define SPI_RX_DMA_THRESHOLD_SHIFT_MASK ((uint8_t)(0x00)) /**< */

/*SPI DMA control register*/
#define SPI_EN_RX_DMA ((uint8_t)( (uint32_t)1))            /**< */
#define SPI_DIS_RX_DMA ((uint8_t)(~SPI_EN_RX_DMA)) /**< */
#define SPI_EN_TX_DMA ((uint8_t)(0x02))            /**< */
#define SPI_DIS_TX_DMA ((uint8_t)(~SPI_EN_TX_DMA))

#endif /* end __SPI__ */

#define __SSI__
#ifdef __SSI__
/*** SSI **********************************************/
/*SSI_CTRLR0*/
#define CTRLR0_DFS_VALUE(x) (x << 0)
#define CTRLR0_FRF_MOT (0x00 << 6)
#define CTRLR0_TMOD_VALUE(x) (x << 10)
#define CTRLR0_TMOD_TX_AND_RX (0x00 << 10)
#define CTRLR0_TMOD_TX_ONLY ( (uint32_t)1 << 10)
#define CTRLR0_TMOD_RX_ONLY (0x02 << 10)
#define CTRLR0_TMOD_EEPROM_READ (0x03 << 10)
#define CTRLR0_CFS_VALUE(x) (x << 16)
#define CTRLR0_SCPH_MASK (1 << 8)
#define CTRLR0_SCPOL_MASK (1 << 9)
#define CTRLR0_SRL_MASK (1 << 13)
#define CTRLR0_SSTE_MASK (1 << 14)
#define CTRLR0_SPI_FRF_STD (0x00 << 22)
#define CTRLR0_SPI_FRF_DUAL ( (uint32_t)1 << 22)
#define CTRLR0_SPI_FRF_QUAD (0x02 << 22)
/*SSIENR*/
#define SSI_EN ((uint8_t)(1 << 0))
/*SPI_CTRLR0*/
#define CTRLR0_TRANS_TYPE_TT0 (0x00 << 0) //Instruction and Address STD mode
#define CTRLR0_TRANS_TYPE_TT1 ( (uint32_t)1 << 0) //Instruction STD mode and Address CTRLR0.SPI_FRF mode
#define CTRLR0_TRANS_TYPE_TT2 (0x02 << 0) //Instruction and Address CTRLR0.SPI_FRF mode
#define CTRLR0_ADDR_L_VALUE(x) (x << 2)
#define CTRLR0_INST_L_VALUE(x) (x << 8)
#define CTRLR0_WAIT_CYCLES_VALUE(x) (x << 11)
#define CTRLR0_CLK_STRETCH_EN_MASK (1 << 30)
#endif

#define __TRNG__
#ifdef __TRNG__
/*** TRNG **********************************************/

#endif /* end __TRNG__ */

#define __TC__
#ifdef __TC__
#define TC_WAIT ((uint8_t)(1 << 11))
#define TC_DOZE ((uint8_t)(1 << 10))
#define TC_STOP ((uint8_t)(1 << 9))
#define TC_DEBUG ((uint8_t)(1 << 8))

#define TC_IF_MODE_MASK ((uint8_t)(1 << 3)) /**< TC */
#define TC_IE_MODE_MASK ((uint8_t)(1 << 2)) /**< TC */
#define TC_CU_MODE_MASK ((uint8_t)(1 << 1)) /**< TC */
#define TC_RN_MODE_MASK ((uint8_t)(1 << 0)) /**< TC */

#endif

#define __UART__
#ifdef __UART__

/*** UART **********************************************/
/*UARTCR1*/
#define UART_WOMS_SHIFT_MASK (6)
#define UART_PARITY_ODD ((uint8_t)(1 << 0))             /**<*/
#define UART_PARITY_EVEN ((uint8_t)(0xFE))              /**<*/
#define UART_PARITY_ENABLE ((uint8_t)(1 << 1))          /**<*/
#define UART_PARITY_DISABLE ((uint8_t)(0xFD))           /**<*/
#define UART_IDLE_LINE_AFTER_STOP ((uint8_t)(1 << 2))   /**<*/
#define UART_IDLE_LINE_AFTER_START ((uint8_t)(0xFB))    /**<*/
#define UART_WAKEUP_MODE_ADDRESS ((uint8_t)(1 << 3))    /**<*/
#define UART_WAKEUP_IDLE_LINE ((uint8_t)(0xF7))         /**<*/
#define UART_DATA_FORMAT_MODE_9BITS ((uint8_t)(1 << 4)) /**<*/
#define UART_DATA_FORMAT_MODE_8BITS ((uint8_t)(0xEF))   /**<*/
#define UART_RSCR_TO_TXD ((uint8_t)(1 << 5))            /**<*/
#define UART_RSCR_TRANSMITTER_OUTPUT ((uint8_t)(0xDF))  /**<*/
#define UART_OPEN_DRAIN_MODE ((uint8_t)(1 << 6))        /**<*/
#define UART_CMOS_MODE ((uint8_t)(0xBF))                /**<*/
#define UART_LOOPS_MODE ((uint8_t)(1 << 7))             /**<*/
#define UART_LOOPS_NORMAL_MODE ((uint8_t)(0x7F))        /**<*/

/*UARTCR2*/
#define UART_SBK ((uint8_t)(1 << 0))           /**<*/
#define UART_IT_RWU_ASLEEP ((uint8_t)(1 << 1)) /**<*/
#define UART_RE ((uint8_t)(1 << 2))            /**<*/
#define UART_TE ((uint8_t)(1 << 3))            /**<*/
#define UART_IT_IDLE ((uint8_t)(1 << 4))       /**<*/
#define UART_IT_RIE ((uint8_t)(1 << 5))        /**<*/
#define UART_IT_TCIE ((uint8_t)(1 << 6))       /**<*/
#define UART_IT_TIE ((uint8_t)(1 << 7))        /**<*/

/*UARTSR1*/
#define UART_IT_FLAG_PF ((uint8_t)(1 << 0))   /**<*/
#define UART_IT_FLAG_FE ((uint8_t)(1 << 1))   /**<*/
#define UART_IT_FLAG_NF ((uint8_t)(1 << 2))   /**<*/
#define UART_IT_FLAG_OR ((uint8_t)(1 << 3))   /**<*/
#define UART_IT_FLAG_IDLE ((uint8_t)(1 << 4)) /**<*/
#define UART_IT_FLAG_RDRF ((uint8_t)(1 << 5)) /**<*/
#define UART_IT_FLAG_TC ((uint8_t)(1 << 6))   /**<*/
#define UART_IT_FLAG_TDRE ((uint8_t)(1 << 7)) /**<*/

/*UARTSR2*/
#define UART_IT_FLAG_RAF ((uint8_t)(1 << 0)) /**<*/

/*UARTPUD*/
#define UART_PU_SHIFT_MASK (0)                 /**<*/
#define UART_PULLUP_EN ((uint8_t)(1 << 0))     /**<*/
#define UART_PULLUP_DIS ((uint8_t)(0xFE))      /**<*/
#define UART_REDUCE_DRIVE ((uint8_t)(1 << 4))  /**<*/
#define UART_FULL_DRIVE ((uint8_t)(0xEF))      /**<*/
#define UART_DOZE_MODE_DIS ((uint8_t)(1 << 7)) /**<*/
#define UART_DOZE_MODE_EN ((uint8_t)(0x7F))    /**<*/

/*UARTDDR:UART data direction register*/
#define UART_RXD_OUT ((uint8_t)(1 << 0)) /**<*/
#define UART_TXD_OUT ((uint8_t)(1 << 1)) /**<*/

/*UARTIRCR:UART infrared control register*/
#define UART_IR_EN ((uint8_t)(1 << 0))            /**<*/
#define UART_IRSC_SYS_CLK ((uint8_t)(1 << 1))     /**<*/
#define UART_RINV_ACTIVE_HIGH ((uint8_t)(1 << 2)) /**<*/
#define UART_TINV_ACTIVE_HIGH ((uint8_t)(1 << 3)) /**<*/
#define UART_RNUM_MASK ((uint8_t)(0xCF))          /**<*/
#define UART_RNUM_SHIFT_MASK ((uint8_t)(4))       /**<*/
#define UART_RNUM_BITS_MASK ((uint8_t)(0x30))     /**<*/
#define UART_TNUM_MASK ((uint8_t)(0x3F))          /**<*/
#define UART_TNUM_SHIFT_MASK ((uint8_t)(6))       /**<*/
#define UART_TNUM_BITS_MASK ((uint8_t)(0xC0))     /**<*/

/*UARTFCR:UART fifo control register*/
#define UART_TF_EN ((uint8_t)(1 << 6))            /**<*/
#define UART_RF_EN ((uint8_t)(1 << 7))            /**<*/
#define UART_RX_FLSEL_MASK ((uint8_t)(0x38))      /**<*/
#define UART_RX_FLSEL_SHIFT_MASK ((uint8_t)(3))   /**<*/
#define UART_RX_FLSEL_BITS_MASK ((uint8_t)(0xC7)) /**<*/
#define UART_TX_FLSEL_MASK ((uint8_t)(0x07))      /**<*/
#define UART_TX_FLSEL_SHIFT_MASK ((uint8_t)(0))   /**<*/
#define UART_TX_FLSEL_BITS_MASK ((uint8_t)(0xF8)) /**<*/

/*UARTFSR:UART FIFO status register*/
#define UART_FIFO_FLAG_R_EMPTY ((uint8_t)(1 << 0)) /**<*/
#define UART_FIFO_FLAG_R_FULL ((uint8_t)(1 << 1))  /**<*/
#define UART_FIFO_FLAG_T_EMPTY ((uint8_t)(1 << 2)) /**<*/
#define UART_FIFO_FLAG_T_FULL ((uint8_t)(1 << 3))  /**<*/
#define UART_FIFO_FLAG_RTOS ((uint8_t)(1 << 4))    /**<*/
#define UART_FIFO_FLAG_RFTS ((uint8_t)(1 << 5))    /**<*/
#define UART_FIFO_FLAG_FTC ((uint8_t)(1 << 6))     /**<*/
#define UART_FIFO_FLAG_TFTS ((uint8_t)(1 << 7))    /**< */

/*UARTDCR:UART DMA control register*/
#define UART_RX_DMA_EN ((uint8_t)(1 << 0)) /**/
#define UART_TX_DMA_EN ((uint8_t)(1 << 1)) /**/

/*UARTFCR2:UART fifo control register 2*/
#define UART_FIFO_RXF_CLR ((uint8_t)(1 << 0))   /**<*/
#define UART_FIFO_TXF_CLR ((uint8_t)(1 << 1))   /**<*/
#define UART_FIFO_RXF_TO_EN ((uint8_t)(1 << 2)) /**<*/
#define UART_FIFO_RXFTO_IE ((uint8_t)(1 << 3))  /**<*/
#define UART_FIFO_RXFOR_IE ((uint8_t)(1 << 4))  /**<*/
#define UART_FIFO_RXF_IE ((uint8_t)(1 << 5))    /**<*/
#define UART_FIFO_TXFC_IE ((uint8_t)(1 << 6))   /**<*/
#define UART_FIFO_TXF_IE ((uint8_t)(1 << 7))    /**<*/

/*UARTFSR2:UART FIFO status register 2*/
#define UART_FXPF ((uint8_t)(1 << 0)) /**<*/
#define UART_FXFE ((uint8_t)(1 << 1)) /**<*/
#define UART_FXNF ((uint8_t)(1 << 2)) /**<*/
#define UART_FXOR ((uint8_t)(1 << 3))

#endif /* end ___ */

#define __WDT__
#ifdef __WDT__

#define WDT_EN (1 << 0)
#define WDT_DEBUG (1 << 1)
#define WDT_DOZE (1 << 2)
#define WDT_WAIT (1 << 3)

#endif /* end __WDT__ */

#define __PWMT__
#ifdef __PWMT__
    /*****************  Bit definition for PWMT register  *****************/
    /*
#define PWM_PPR_DZ1_SHIFT                 24     
#define PWM_PPR_DZ0_SHIFT                 16
#define PWM_PPR_CP1_SHIFT                 8     
#define PWM_PPR_CP0_SHIFT                 0     
 
#define PWM_PCSR_CSR7_SHIFT               28    
#define PWM_PCSR_CSR6_SHIFT               24     
#define PWM_PCSR_CSR5_SHIFT               20     
#define PWM_PCSR_CSR4_SHIFT               16  
#define PWM_PCSR_CSR3_SHIFT               12    
#define PWM_PCSR_CSR2_SHIFT               8     
#define PWM_PCSR_CSR1_SHIFT               4     
#define PWM_PCSR_CSR0_SHIFT               0     

#define PWM_PCR_CH0EN                     (1<<0)
#define PWM_PCR_CH0INV                    (1<<2)
#define PWM_PCR_CH0MOD                    (1<<3)
#define PWM_PCR_DZ0EN                     (1<<4)
#define PWM_PCR_DZ1EN                     (1<<5)
#define PWM_PCR_CH1EN                     (1<<8)
#define PWM_PCR_CH1INV                    (1<<10)
#define PWM_PCR_CH1MOD                    (1<<11)
#define PWM_PCR_CH2EN                     (1<<16)
#define PWM_PCR_CH2INV                    (1<<18)
#define PWM_PCR_CH2MOD                    (1<<19)
#define PWM_PCR_CH3EN                     (1<<24)
#define PWM_PCR_CH3INV                    (1<<26)
#define PWM_PCR_CH3MOD                    (1<<27)
#define PWM_PCR_CH4EN                     (1<<1)
#define PWM_PCR_CH5EN                     (1<<9)
#define PWM_PCR_CH6EN                     (1<<17)
#define PWM_PCR_CH7EN                     (1<<25)
*/

#define PWMT_CR1_CKD_00 (00 << 8)
#define PWMT_CR1_CKD_01 (01 << 8)
#define PWMT_CR1_CKD_10 (10 << 8)
#define PWMT_CR1_ARPE (1 << 7)
#define PWMT_CR1_CMS_EALIGN (0 << 5)
#define PWMT_CR1_CMS_CALIGN1 (1 << 5)
#define PWMT_CR1_CMS_CALIGN2 (2 << 5)
#define PWMT_CR1_CMS_CALIGN3 (3 << 5)
#define PWMT_CR1_DIR_UP (0 << 4)
#define PWMT_CR1_DIR_DOWN (1 << 4)
#define PWMT_CR1_OPM (1 << 3)
#define PWMT_CR1_URS (1 << 2)
#define PWMT_CR1_UDIS (1 << 1)
#define PWMT_CR1_CEN (1 << 0)

#define PWMT_CR2_OIS4N (1 << 15)
#define PWMT_CR2_OIS4 (1 << 14)
#define PWMT_CR2_OIS3N (1 << 13)
#define PWMT_CR2_OIS3 (1 << 12)
#define PWMT_CR2_OIS2N (1 << 11)
#define PWMT_CR2_OIS2 (1 << 10)
#define PWMT_CR2_OIS1N (1 << 9)
#define PWMT_CR2_OIS1 (1 << 8)
#define PWMT_CR2_TI1S (1 << 7)
#define PWMT_CR2_MMS_RESET (0 << 4)
#define PWMT_CR2_MMS_ENABLE (1 << 4)
#define PWMT_CR2_MMS_UPDATE (2 << 4)
#define PWMT_CR2_MMS_COMPP (3 << 4)
#define PWMT_CR2_MMS_COMP1TRGO (4 << 4)
#define PWMT_CR2_MMS_COMP2TRGO (5 << 4)
#define PWMT_CR2_MMS_COMP3TRGO (6 << 4)
#define PWMT_CR2_MMS_COMP4TRGO (7 << 4)
#define PWMT_CR2_CCDS (1 << 2)
#define PWMT_CR2_CCUS (1 << 1)
#define PWMT_CR2_CCPC (1 << 0)

#define PWMT_SMCR_ETP (1 << 15)
#define PWMT_SMCR_ECE (1 << 14)
#define PWMT_SMCR_ETPS_PRESCOFF (0 << 12)
#define PWMT_SMCR_ETPS_PRESCDIV2 (1 << 12)
#define PWMT_SMCR_ETPS_PRESCDIV4 (2 << 12)
#define PWMT_SMCR_ETPS_PRESCDIV8 (3 << 12)
#define PWMT_SMCR_ETF_D1_N1 (00 << 8)
#define PWMT_SMCR_ETF_D1_N2 (01 << 8)
#define PWMT_SMCR_ETF_D1_N4 (02 << 8)
#define PWMT_SMCR_ETF_D1_N8 (03 << 8)
#define PWMT_SMCR_ETF_D2_N6 (04 << 8)
#define PWMT_SMCR_ETF_D2_N8 (05 << 8)
#define PWMT_SMCR_ETF_D4_N6 (06 << 8)
#define PWMT_SMCR_ETF_D4_N8 (07 << 8)
#define PWMT_SMCR_ETF_D8_N6 (08 << 8)
#define PWMT_SMCR_ETF_D8_N8 (09 << 8)
#define PWMT_SMCR_ETF_D16_N5 (10 << 8)
#define PWMT_SMCR_ETF_D16_N6 (11 << 8)
#define PWMT_SMCR_ETF_D16_N8 (12 << 8)
#define PWMT_SMCR_ETF_D32_N5 (13 << 8)
#define PWMT_SMCR_ETF_D32_N6 (14 << 8)
#define PWMT_SMCR_ETF_D32_N8 (15 << 8)
#define PWMT_SMCR_MSM (1 << 7)
#define PWMT_SMCR_TS_TRGI0 (0 << 4)
#define PWMT_SMCR_TS_TRGI1 (1 << 4)
#define PWMT_SMCR_TS_TRGI2 (2 << 4)
#define PWMT_SMCR_TS_TRGI3 (3 << 4)
#define PWMT_SMCR_TS_TI1F_ED (4 << 4)
#define PWMT_SMCR_TS_TI1FP1 (5 << 4)
#define PWMT_SMCR_TS_TI2FP2 (6 << 4)
#define PWMT_SMCR_TS_ETRF (7 << 4)
#define PWMT_SMCR_SMS_SLV_DIS (0 << 0) //disable slave ??
#define PWMT_SMCR_SMS_ENC_MODE1 (1 << 0)
#define PWMT_SMCR_SMS_ENC_MODE2 (2 << 0)
#define PWMT_SMCR_SMS_ENC_MODE3 (3 << 0)
#define PWMT_SMCR_SMS_RESET (4 << 0)   //??��??
#define PWMT_SMCR_SMS_GATED (5 << 0)   //?????
#define PWMT_SMCR_SMS_TRIGGER (6 << 0) //??????
#define PWMT_SMCR_SMS_EXTCLK (7 << 0)

#define PWMT_DIER_TDE (1 << 14)
#define PWMT_DIER_COMDE (1 << 13)
#define PWMT_DIER_CC4DE (1 << 12)
#define PWMT_DIER_CC3DE (1 << 11)
#define PWMT_DIER_CC2DE (1 << 10)
#define PWMT_DIER_CC1DE (1 << 9)
#define PWMT_DIER_UDE (1 << 8)
#define PWMT_DIER_BIE (1 << 7)
#define PWMT_DIER_TIE (1 << 6)
#define PWMT_DIER_COMIE (1 << 5)
#define PWMT_DIER_CC4IE (1 << 4)
#define PWMT_DIER_CC3IE (1 << 3)
#define PWMT_DIER_CC2IE (1 << 2)
#define PWMT_DIER_CC1IE (1 << 1)
#define PWMT_DIER_UIE (1 << 0)

#define PWMT_SR_CC4OF (1 << 12)
#define PWMT_SR_CC3OF (1 << 11)
#define PWMT_SR_CC2OF (1 << 10)
#define PWMT_SR_CC1OF (1 << 9)
#define PWMT_SR_BIF (1 << 7)
#define PWMT_SR_TIF (1 << 6)
#define PWMT_SR_COMIF (1 << 5)
#define PWMT_SR_CC4IF (1 << 4)
#define PWMT_SR_CC3IF (1 << 3)
#define PWMT_SR_CC2IF (1 << 2)
#define PWMT_SR_CC1IF (1 << 1)
#define PWMT_SR_UIF (1 << 0)

#define PWMT_EGR_BG (1 << 7)
#define PWMT_EGR_TG (1 << 6)
#define PWMT_EGR_COMG (1 << 5)
#define PWMT_EGR_CC4G (1 << 4)
#define PWMT_EGR_CC3G (1 << 3)
#define PWMT_EGR_CC2G (1 << 2)
#define PWMT_EGR_CC1G (1 << 1)
#define PWMT_EGR_UG (1 << 0)

#define PWMT_CCMR1_OC2CE (1 << 15)
#define PWMT_CCMR1_OC2M_FROZEN (0 << 12)
#define PWMT_CCMR1_OC2M_ACT_MATCH (1 << 12)
#define PWMT_CCMR1_OC2M_INACT_MATCH (2 << 12)
#define PWMT_CCMR1_OC2M_TOGGLE (3 << 12)
#define PWMT_CCMR1_OC2M_FORCE_ACT_LVL (4 << 12)
#define PWMT_CCMR1_OC2M_FORCE_INACT_LVL (5 << 12)
#define PWMT_CCMR1_OC2M_PWM_MODE1 (6 << 12)
#define PWMT_CCMR1_OC2M_PWM_MODE2 (7 << 12)
#define PWMT_CCMR1_OC2PE (1 << 11)
#define PWMT_CCMR1_OC2FE (1 << 10)
#define PWMT_CCMR1_CC2S_OUT (0 << 8)
#define PWMT_CCMR1_CC2S_IN_IC2_TI2 (1 << 8)
#define PWMT_CCMR1_CC2S_IN_IC2_TI1 (2 << 8)
#define PWMT_CCMR1_CC2S_IN_IC2_TRC (3 << 8)
#define PWMT_CCMR1_OC1CE (1 << 7)
#define PWMT_CCMR1_OC1M_FROZEN (0 << 4)
#define PWMT_CCMR1_OC1M_ACT_MATCH (1 << 4)
#define PWMT_CCMR1_OC1M_INACT_MATCH (2 << 4)
#define PWMT_CCMR1_OC1M_TOGGLE (3 << 4)
#define PWMT_CCMR1_OC1M_FORCE_ACT_LVL (4 << 4)
#define PWMT_CCMR1_OC1M_FORCE_INACT_LVL (5 << 4)
#define PWMT_CCMR1_OC1M_PWM_MODE1 (6 << 4)
#define PWMT_CCMR1_OC1M_PWM_MODE2 (7 << 4)
#define PWMT_CCMR1_OC1PE (1 << 3)
#define PWMT_CCMR1_OC1FE (1 << 2)
#define PWMT_CCMR1_CC1S_OUT (0 << 0)
#define PWMT_CCMR1_CC1S_IN_IC1_TI1 (1 << 0)
#define PWMT_CCMR1_CC1S_IN_IC1_TI2 (2 << 0)
#define PWMT_CCMR1_CC1S_IN_IC1_TRC (3 << 0)
#define PWMT_CCMR1_IC2F_D1_N1 (00 << 12)
#define PWMT_CCMR1_IC2F_D1_N2 (01 << 12)
#define PWMT_CCMR1_IC2F_D1_N4 (02 << 12)
#define PWMT_CCMR1_IC2F_D1_N8 (03 << 12)
#define PWMT_CCMR1_IC2F_D2_N6 (04 << 12)
#define PWMT_CCMR1_IC2F_D2_N8 (05 << 12)
#define PWMT_CCMR1_IC2F_D4_N6 (06 << 12)
#define PWMT_CCMR1_IC2F_D4_N8 (07 << 12)
#define PWMT_CCMR1_IC2F_D8_N6 (08 << 12)
#define PWMT_CCMR1_IC2F_D8_N8 (09 << 12)
#define PWMT_CCMR1_IC2F_D16_N5 (10 << 12)
#define PWMT_CCMR1_IC2F_D16_N6 (11 << 12)
#define PWMT_CCMR1_IC2F_D16_N8 (12 << 12)
#define PWMT_CCMR1_IC2F_D32_N5 (13 << 12)
#define PWMT_CCMR1_IC2F_D32_N6 (14 << 12)
#define PWMT_CCMR1_IC2F_D32_N8 (15 << 12)
#define PWMT_CCMR1_IC2PSC_D1 (0 << 10)
#define PWMT_CCMR1_IC2PSC_D2 (1 << 10)
#define PWMT_CCMR1_IC2PSC_D4 (2 << 10)
#define PWMT_CCMR1_IC2PSC_D8 (3 << 10)
#define PWMT_CCMR1_IC1F_D1_N1 (00 << 4)
#define PWMT_CCMR1_IC1F_D1_N2 (01 << 4)
#define PWMT_CCMR1_IC1F_D1_N4 (02 << 4)
#define PWMT_CCMR1_IC1F_D1_N8 (03 << 4)
#define PWMT_CCMR1_IC1F_D2_N6 (04 << 4)
#define PWMT_CCMR1_IC1F_D2_N8 (05 << 4)
#define PWMT_CCMR1_IC1F_D4_N6 (06 << 4)
#define PWMT_CCMR1_IC1F_D4_N8 (07 << 4)
#define PWMT_CCMR1_IC1F_D8_N6 (08 << 4)
#define PWMT_CCMR1_IC1F_D8_N8 (09 << 4)
#define PWMT_CCMR1_IC1F_D16_N5 (10 << 4)
#define PWMT_CCMR1_IC1F_D16_N6 (11 << 4)
#define PWMT_CCMR1_IC1F_D16_N8 (12 << 4)
#define PWMT_CCMR1_IC1F_D32_N5 (13 << 4)
#define PWMT_CCMR1_IC1F_D32_N6 (14 << 4)
#define PWMT_CCMR1_IC1F_D32_N8 (15 << 4)
#define PWMT_CCMR1_IC1PSC_D1 (0 << 2)
#define PWMT_CCMR1_IC1PSC_D2 (1 << 2)
#define PWMT_CCMR1_IC1PSC_D4 (2 << 2)
#define PWMT_CCMR1_IC1PSC_D8 (3 << 2)

#define PWMT_CCMR2_OC4CE (1 << 15)
#define PWMT_CCMR2_OC4M_FROZEN (0 << 12)
#define PWMT_CCMR2_OC4M_ACT_MATCH (1 << 12)
#define PWMT_CCMR2_OC4M_INACT_MATCH (2 << 12)
#define PWMT_CCMR2_OC4M_TOGGLE (3 << 12)
#define PWMT_CCMR2_OC4M_FORCE_ACT_LVL (4 << 12)
#define PWMT_CCMR2_OC4M_FORCE_INACT_LVL (5 << 12)
#define PWMT_CCMR2_OC4M_PWM_MODE1 (6 << 12)
#define PWMT_CCMR2_OC4M_PWM_MODE2 (7 << 12)
#define PWMT_CCMR2_OC4PE (1 << 11)
#define PWMT_CCMR2_OC4FE (1 << 10)
#define PWMT_CCMR2_CC4S_OUT (0 << 8)
#define PWMT_CCMR2_CC4S_IN_IC4_TI4 (1 << 8)
#define PWMT_CCMR2_CC4S_IN_IC4_TI3 (2 << 8)
#define PWMT_CCMR2_CC4S_IN_IC4_TRC (3 << 8)
#define PWMT_CCMR2_OC3CE (1 << 7)
#define PWMT_CCMR2_OC3M_FROZEN (0 << 4)
#define PWMT_CCMR2_OC3M_ACT_MATCH (1 << 4)
#define PWMT_CCMR2_OC3M_INACT_MATCH (2 << 4)
#define PWMT_CCMR2_OC3M_TOGGLE (3 << 4)
#define PWMT_CCMR2_OC3M_FORCE_ACT_LVL (4 << 4)
#define PWMT_CCMR2_OC3M_FORCE_INACT_LVL (5 << 4)
#define PWMT_CCMR2_OC3M_PWM_MODE1 (6 << 4)
#define PWMT_CCMR2_OC3M_PWM_MODE2 (7 << 4)
#define PWMT_CCMR2_OC3PE (1 << 3)
#define PWMT_CCMR2_OC3FE (1 << 2)
#define PWMT_CCMR2_CC3S_OUT (0 << 0)
#define PWMT_CCMR2_CC3S_IN_IC3_TI3 (1 << 0)
#define PWMT_CCMR2_CC3S_IN_IC3_TI4 (2 << 0)
#define PWMT_CCMR2_CC3S_IN_IC3_TRC (3 << 0)
#define PWMT_CCMR2_IC4F_D1_N1 (00 << 12)
#define PWMT_CCMR2_IC4F_D1_N2 (01 << 12)
#define PWMT_CCMR2_IC4F_D1_N4 (02 << 12)
#define PWMT_CCMR2_IC4F_D1_N8 (03 << 12)
#define PWMT_CCMR2_IC4F_D2_N6 (04 << 12)
#define PWMT_CCMR2_IC4F_D2_N8 (05 << 12)
#define PWMT_CCMR2_IC4F_D4_N6 (06 << 12)
#define PWMT_CCMR2_IC4F_D4_N8 (07 << 12)
#define PWMT_CCMR2_IC4F_D8_N6 (08 << 12)
#define PWMT_CCMR2_IC4F_D8_N8 (09 << 12)
#define PWMT_CCMR2_IC4F_D16_N5 (10 << 12)
#define PWMT_CCMR2_IC4F_D16_N6 (11 << 12)
#define PWMT_CCMR2_IC4F_D16_N8 (12 << 12)
#define PWMT_CCMR2_IC4F_D32_N5 (13 << 12)
#define PWMT_CCMR2_IC4F_D32_N6 (14 << 12)
#define PWMT_CCMR2_IC4F_D32_N8 (15 << 12)
#define PWMT_CCMR2_IC4PSC_D1 (0 << 10)
#define PWMT_CCMR2_IC4PSC_D2 (1 << 10)
#define PWMT_CCMR2_IC4PSC_D4 (2 << 10)
#define PWMT_CCMR2_IC4PSC_D8 (3 << 10)
#define PWMT_CCMR2_IC3F_D1_N1 (00 << 4)
#define PWMT_CCMR2_IC3F_D1_N2 (01 << 4)
#define PWMT_CCMR2_IC3F_D1_N4 (02 << 4)
#define PWMT_CCMR2_IC3F_D1_N8 (03 << 4)
#define PWMT_CCMR2_IC3F_D2_N6 (04 << 4)
#define PWMT_CCMR2_IC3F_D2_N8 (05 << 4)
#define PWMT_CCMR2_IC3F_D4_N6 (06 << 4)
#define PWMT_CCMR2_IC3F_D4_N8 (07 << 4)
#define PWMT_CCMR2_IC3F_D8_N6 (08 << 4)
#define PWMT_CCMR2_IC3F_D8_N8 (09 << 4)
#define PWMT_CCMR2_IC3F_D16_N5 (10 << 4)
#define PWMT_CCMR2_IC3F_D16_N6 (11 << 4)
#define PWMT_CCMR2_IC3F_D16_N8 (12 << 4)
#define PWMT_CCMR2_IC3F_D32_N5 (13 << 4)
#define PWMT_CCMR2_IC3F_D32_N6 (14 << 4)
#define PWMT_CCMR2_IC3F_D32_N8 (15 << 4)
#define PWMT_CCMR2_IC3PSC_D1 (0 << 2)
#define PWMT_CCMR2_IC3PSC_D2 (1 << 2)
#define PWMT_CCMR2_IC3PSC_D4 (2 << 2)
#define PWMT_CCMR2_IC3PSC_D8 (3 << 2)

#define PWMT_CCER_CC4NP (1 << 15)
#define PWMT_CCER_CC4NE (1 << 14)
#define PWMT_CCER_CC4P (1 << 13)
#define PWMT_CCER_CC4E (1 << 12)
#define PWMT_CCER_CC3NP (1 << 11)
#define PWMT_CCER_CC3NE (1 << 10)
#define PWMT_CCER_CC3P (1 << 9)
#define PWMT_CCER_CC3E (1 << 8)
#define PWMT_CCER_CC2NP (1 << 7)
#define PWMT_CCER_CC2NE (1 << 6)
#define PWMT_CCER_CC2P (1 << 5)
#define PWMT_CCER_CC2E (1 << 4)
#define PWMT_CCER_CC1NP (1 << 3)
#define PWMT_CCER_CC1NE (1 << 2)
#define PWMT_CCER_CC1P (1 << 1)
#define PWMT_CCER_CC1E (1 << 0)

#define PWMT_BDTR_MOE (1 << 15)
#define PWMT_BDTR_AOE (1 << 14)
#define PWMT_BDTR_BKP (1 << 13)
#define PWMT_BDTR_BKE (1 << 12)
#define PWMT_BDTR_OSSR (1 << 11)
#define PWMT_BDTR_OSSI (1 << 10)
#define PWMT_BDTR_LOCK_OFF (0 << 8)
#define PWMT_BDTR_LOCK_LEVEL1 (1 << 8)
#define PWMT_BDTR_LOCK_LEVEL2 (2 << 8)
#define PWMT_BDTR_LOCK_LEVEL3 (3 << 8)

#define PWMT_PMCR1_EN (1 << 0)
#define PWMT_PMCR1_RELA_EN (1 << 1)
#define PWMT_PMCR1N_RELA_EN (1 << 2)
#define PWMT_PMCR2_EN (1 << 3)
#define PWMT_PMCR2_RELA_EN (1 << 4)
#define PWMT_PMCR2N_RELA_EN (1 << 5)
#define PWMT_PMCR3_EN (1 << 6)
#define PWMT_PMCR3_RELA_EN (1 << 7)
#define PWMT_PMCR3N_RELA_EN (1 << 8)
#define PWMT_PMCR4_EN (1 << 9)
#define PWMT_PMCR4_RELA_EN (1 << 10)
#define PWMT_PMCR4N_RELA_EN (1 << 11)

#define BIT_CKD (8)
#define BIT_ARPE (7)
#define BIT_CMS (5)
#define BIT_DIR (4)
#define BIT_DIR (4)
#define BIT_OPM (3)
#define BIT_URS (2)
#define BIT_UDIS (1)
#define BIT_CEN (0)

#define BIT_OIS4N (15)
#define BIT_OIS4 (14)
#define BIT_OIS3N (13)
#define BIT_OIS3 (12)
#define BIT_OIS2N (11)
#define BIT_OIS2 (10)
#define BIT_OIS1N (9)
#define BIT_OIS1 (8)
#define BIT_TI1S (7)
#define BIT_MMS (4)
#define BIT_CCDS (3)
#define BIT_CCUS (2)
#define BIT_CCPC (0)

#define BIT_ETP (15)
#define BIT_ECE (14)
#define BIT_ETPS (12)
#define BIT_ETF (8)
#define BIT_MSM (7)
#define BIT_TS (4)
#define BIT_SMS (0)

#define BIT_TDE (14)
#define BIT_COMDE (13)
#define BIT_CC4DE (12)
#define BIT_CC3DE (11)
#define BIT_CC2DE (10)
#define BIT_CC1DE (9)
#define BIT_UDE (8)
#define BIT_BIE (7)
#define BIT_TIE (6)
#define BIT_COMIE (5)
#define BIT_CC4IE (4)
#define BIT_CC3IE (3)
#define BIT_CC2IE (2)
#define BIT_CC1IE (1)
#define BIT_UIE (0)

#define BIT_CC4OF (12)
#define BIT_CC3OF (11)
#define BIT_CC2OF (10)
#define BIT_CC1OF (9)
#define BIT_BIF (7)
#define BIT_TIF (6)
#define BIT_COMIF (5)
#define BIT_CC4IF (4)
#define BIT_CC3IF (3)
#define BIT_CC2IF (2)
#define BIT_CC1IF (1)
#define BIT_UIF (0)

#define BIT_BG (7)
#define BIT_TG (6)
#define BIT_COMG (5)
#define BIT_CC4G (4)
#define BIT_CC3G (3)
#define BIT_CC2G (2)
#define BIT_CC1G (1)
#define BIT_UG (0)

#define BIT_OC2CE (15)
#define BIT_OC2M (12)
#define BIT_OC2PE (11)
#define BIT_OC2FE (10)
#define BIT_CC2S (8)
#define BIT_OC1CE (7)
#define BIT_OC1M (4)
#define BIT_OC1PE (3)
#define BIT_OC1FE (2)
#define BIT_CC1S (0)
#define BIT_IC2F (12)
#define BIT_IC2PSC (10)
#define BIT_IC1F (4)
#define BIT_IC1PSC (2)

#define BIT_OC4CE (15)
#define BIT_OC4M (12)
#define BIT_OC4PE (11)
#define BIT_OC4FE (10)
#define BIT_CC4S (8)
#define BIT_OC3CE (7)
#define BIT_OC3M (4)
#define BIT_OC3PE (3)
#define BIT_OC3FE (2)
#define BIT_CC3S (0)
#define BIT_IC4F (12)
#define BIT_IC4PSC (10)
#define BIT_IC3F (4)
#define BIT_IC3PSC (2)

#define BIT_CC4NP (15)
#define BIT_CC4NE (14)
#define BIT_CC4P (13)
#define BIT_CC4E (12)
#define BIT_CC3NP (11)
#define BIT_CC3NE (10)
#define BIT_CC3P (9)
#define BIT_CC3E (8)
#define BIT_CC2NP (7)
#define BIT_CC2NE (6)
#define BIT_CC2P (5)
#define BIT_CC2E (4)
#define BIT_CC1NP (3)
#define BIT_CC1NE (2)
#define BIT_CC1P (1)
#define BIT_CC1E (0)

#define CR1_CKD_00 (0)
#define CR1_CKD_01 (1)
#define CR1_CKD_10 (10)
#define CR1_ARPE (1)
#define CR1_CMS_EALIGN (0)
#define CR1_CMS_CALIGN1 (1)
#define CR1_CMS_CALIGN2 (2)
#define CR1_CMS_CALIGN3 (3)
#define CR1_DIR_UP (0)
#define CR1_DIR_DOWN (1)
#define CR1_OPM (1)
#define CR1_URS (1)
#define CR1_UDIS (1)
#define CR1_CEN (1)

#define CR2_OIS4N (1)
#define CR2_OIS4 (1)
#define CR2_OIS3N (1)
#define CR2_OIS3 (1)
#define CR2_OIS2N (1)
#define CR2_OIS2 (1)
#define CR2_OIS1N (1)
#define CR2_OIS1 (1)
#define CR2_TI1S (1)
#define CR2_MMS_RESET (0)
#define CR2_MMS_ENABLE (1)
#define CR2_MMS_UPDATE (2)
#define CR2_MMS_COMPP (3)
#define CR2_MMS_COMP1TRGO (4)
#define CR2_MMS_COMP2TRGO (5)
#define CR2_MMS_COMP3TRGO (6)
#define CR2_MMS_COMP4TRGO (7)
#define CR2_CCDS (1)
#define CR2_CCUS (1)
#define CR2_CCPC (1)

#define SMCR_ETP (1)
#define SMCR_ECE (1)
#define SMCR_ETPS_PRESCOFF (0)
#define SMCR_ETPS_PRESCDIV2 (1)
#define SMCR_ETPS_PRESCDIV4 (2)
#define SMCR_ETPS_PRESCDIV8 (3)
#define SMCR_ETF_D1_N1 (0)
#define SMCR_ETF_D1_N2 (1)
#define SMCR_ETF_D1_N4 (2)
#define SMCR_ETF_D1_N8 (3)
#define SMCR_ETF_D2_N6 (4)
#define SMCR_ETF_D2_N8 (5)
#define SMCR_ETF_D4_N6 (6)
#define SMCR_ETF_D4_N8 (7)
#define SMCR_ETF_D8_N6 (8)
#define SMCR_ETF_D8_N8 (9)
#define SMCR_ETF_D16_N5 (10)
#define SMCR_ETF_D16_N6 (11)
#define SMCR_ETF_D16_N8 (12)
#define SMCR_ETF_D32_N5 (13)
#define SMCR_ETF_D32_N6 (14)
#define SMCR_ETF_D32_N8 (15)
#define SMCR_MSM (1)
#define SMCR_TS_TRGI0 (0)
#define SMCR_TS_TRGI1 (1)
#define SMCR_TS_TRGI2 (2)
#define SMCR_TS_TRGI3 (3)
#define SMCR_TS_TI1F_ED (4)
#define SMCR_TS_TI1FP1 (5)
#define SMCR_TS_TI2FP2 (6)
#define SMCR_TS_ETRF (7)
#define SMCR_SMS_SLV_DIS (0)
#define SMCR_SMS_ENC_MODE1 (1)
#define SMCR_SMS_ENC_MODE2 (2)
#define SMCR_SMS_ENC_MODE3 (3)
#define SMCR_SMS_RESET (4)
#define SMCR_SMS_GATED (5)
#define SMCR_SMS_TRIGGER (6)
#define SMCR_SMS_EXTCLK (7)

#define DIER_TDE (1)
#define DIER_COMDE (1)
#define DIER_CC4DE (1)
#define DIER_CC3DE (1)
#define DIER_CC2DE (1)
#define DIER_CC1DE (1)
#define DIER_UDE (1)
#define DIER_BIE (1)
#define DIER_TIE (1)
#define DIER_COMIE (1)
#define DIER_CC4IE (1)
#define DIER_CC3IE (1)
#define DIER_CC2IE (1)
#define DIER_CC1IE (1)
#define DIER_UIE (1)

#define SR_CC4OF (1)
#define SR_CC3OF (1)
#define SR_CC2OF (1)
#define SR_CC1OF (1)
#define SR_BIF (1)
#define SR_TIF (1)
#define SR_COMIF (1)
#define SR_CC4IF (1)
#define SR_CC3IF (1)
#define SR_CC2IF (1)
#define SR_CC1IF (1)
#define SR_UIF (1)

#define EGR_BG (1)
#define EGR_TG (1)
#define EGR_COMG (1)
#define EGR_CC4G (1)
#define EGR_CC3G (1)
#define EGR_CC2G (1)
#define EGR_CC1G (1)
#define EGR_UG (1)

#define CCMR1_OC2CE (1)
#define CCMR1_OC2M_FROZEN (0)
#define CCMR1_OC2M_ACT_MATCH (1)
#define CCMR1_OC2M_INACT_MATCH (2)
#define CCMR1_OC2M_TOGGLE (3)
#define CCMR1_OC2M_FORCE_ACT_LVL (4)
#define CCMR1_OC2M_FORCE_INACT_LVL (5)
#define CCMR1_OC2M_PWM_MODE1 (6)
#define CCMR1_OC2M_PWM_MODE2 (7)
#define CCMR1_OC2PE (1)
#define CCMR1_OC2FE (1)
#define CCMR1_CC2S_OUT (0)
#define CCMR1_CC2S_IN_IC2_TI2 (1)
#define CCMR1_CC2S_IN_IC2_TI1 (10)
#define CCMR1_CC2S_IN_IC2_TRC (11)
#define CCMR1_OC1CE (1)
#define CCMR1_OC1M_FROZEN (0)
#define CCMR1_OC1M_ACT_MATCH (1)
#define CCMR1_OC1M_INACT_MATCH (2)
#define CCMR1_OC1M_TOGGLE (3)
#define CCMR1_OC1M_FORCE_ACT_LVL (4)
#define CCMR1_OC1M_FORCE_INACT_LVL (5)
#define CCMR1_OC1M_PWM_MODE1 (6)
#define CCMR1_OC1M_PWM_MODE2 (7)
#define CCMR1_OC1PE (1)
#define CCMR1_OC1FE (1)
#define CCMR1_CC1S_OUT (0)
#define CCMR1_CC1S_IN_IC1_TI1 (1)
#define CCMR1_CC1S_IN_IC1_TI2 (10)
#define CCMR1_CC1S_IN_IC1_TRC (11)
#define CCMR1_IC2F_D1_N1 (0)
#define CCMR1_IC2F_D1_N2 (1)
#define CCMR1_IC2F_D1_N4 (2)
#define CCMR1_IC2F_D1_N8 (3)
#define CCMR1_IC2F_D2_N6 (4)
#define CCMR1_IC2F_D2_N8 (5)
#define CCMR1_IC2F_D4_N6 (6)
#define CCMR1_IC2F_D4_N8 (7)
#define CCMR1_IC2F_D8_N6 (8)
#define CCMR1_IC2F_D8_N8 (9)
#define CCMR1_IC2F_D16_N5 (10)
#define CCMR1_IC2F_D16_N6 (11)
#define CCMR1_IC2F_D16_N8 (12)
#define CCMR1_IC2F_D32_N5 (13)
#define CCMR1_IC2F_D32_N6 (14)
#define CCMR1_IC2F_D32_N8 (15)
#define CCMR1_IC2PSC_D1 (0)
#define CCMR1_IC2PSC_D2 (1)
#define CCMR1_IC2PSC_D4 (10)
#define CCMR1_IC2PSC_D8 (11)
#define CCMR1_IC1F_D1_N1 (0)
#define CCMR1_IC1F_D1_N2 (1)
#define CCMR1_IC1F_D1_N4 (2)
#define CCMR1_IC1F_D1_N8 (3)
#define CCMR1_IC1F_D2_N6 (4)
#define CCMR1_IC1F_D2_N8 (5)
#define CCMR1_IC1F_D4_N6 (6)
#define CCMR1_IC1F_D4_N8 (7)
#define CCMR1_IC1F_D8_N6 (8)
#define CCMR1_IC1F_D8_N8 (9)
#define CCMR1_IC1F_D16_N5 (10)
#define CCMR1_IC1F_D16_N6 (11)
#define CCMR1_IC1F_D16_N8 (12)
#define CCMR1_IC1F_D32_N5 (13)
#define CCMR1_IC1F_D32_N6 (14)
#define CCMR1_IC1F_D32_N8 (15)
#define CCMR1_IC1PSC_D1 (0)
#define CCMR1_IC1PSC_D2 (1)
#define CCMR1_IC1PSC_D4 (10)
#define CCMR1_IC1PSC_D8 (11)

#define CCMR2_OC4CE (1)
#define CCMR2_OC4M_FROZEN (0)
#define CCMR2_OC4M_ACT_MATCH (1)
#define CCMR2_OC4M_INACT_MATCH (2)
#define CCMR2_OC4M_TOGGLE (3)
#define CCMR2_OC4M_FORCE_ACT_LVL (4)
#define CCMR2_OC4M_FORCE_INACT_LVL (5)
#define CCMR2_OC4M_PWM_MODE1 (6)
#define CCMR2_OC4M_PWM_MODE2 (7)
#define CCMR2_OC4PE (1)
#define CCMR2_OC4FE (1)
#define CCMR2_CC4S_OUT (0)
#define CCMR2_CC4S_IN_IC4_TI4 (1)
#define CCMR2_CC4S_IN_IC4_TI3 (10)
#define CCMR2_CC4S_IN_IC4_TRC (11)
#define CCMR2_OC3CE (1)
#define CCMR2_OC3M_FROZEN (0)
#define CCMR2_OC3M_ACT_MATCH (1)
#define CCMR2_OC3M_INACT_MATCH (2)
#define CCMR2_OC3M_TOGGLE (3)
#define CCMR2_OC3M_FORCE_ACT_LVL (4)
#define CCMR2_OC3M_FORCE_INACT_LVL (5)
#define CCMR2_OC3M_PWM_MODE1 (6)
#define CCMR2_OC3M_PWM_MODE2 (7)
#define CCMR2_OC3PE (1)
#define CCMR2_OC3FE (1)
#define CCMR2_CC3S_OUT (0)
#define CCMR2_CC3S_IN_IC3_TI3 (1)
#define CCMR2_CC3S_IN_IC3_TI4 (10)
#define CCMR2_CC3S_IN_IC3_TRC (11)
#define CCMR2_IC4F_D1_N1 (0)
#define CCMR2_IC4F_D1_N2 (1)
#define CCMR2_IC4F_D1_N4 (2)
#define CCMR2_IC4F_D1_N8 (3)
#define CCMR2_IC4F_D2_N6 (4)
#define CCMR2_IC4F_D2_N8 (5)
#define CCMR2_IC4F_D4_N6 (6)
#define CCMR2_IC4F_D4_N8 (7)
#define CCMR2_IC4F_D8_N6 (8)
#define CCMR2_IC4F_D8_N8 (9)
#define CCMR2_IC4F_D16_N5 (10)
#define CCMR2_IC4F_D16_N6 (11)
#define CCMR2_IC4F_D16_N8 (12)
#define CCMR2_IC4F_D32_N5 (13)
#define CCMR2_IC4F_D32_N6 (14)
#define CCMR2_IC4F_D32_N8 (15)
#define CCMR2_IC4PSC_D1 (0)
#define CCMR2_IC4PSC_D2 (1)
#define CCMR2_IC4PSC_D4 (10)
#define CCMR2_IC4PSC_D8 (11)
#define CCMR2_IC3F_D1_N1 (0)
#define CCMR2_IC3F_D1_N2 (1)
#define CCMR2_IC3F_D1_N4 (2)
#define CCMR2_IC3F_D1_N8 (3)
#define CCMR2_IC3F_D2_N6 (4)
#define CCMR2_IC3F_D2_N8 (5)
#define CCMR2_IC3F_D4_N6 (6)
#define CCMR2_IC3F_D4_N8 (7)
#define CCMR2_IC3F_D8_N6 (8)
#define CCMR2_IC3F_D8_N8 (9)
#define CCMR2_IC3F_D16_N5 (10)
#define CCMR2_IC3F_D16_N6 (11)
#define CCMR2_IC3F_D16_N8 (12)
#define CCMR2_IC3F_D32_N5 (13)
#define CCMR2_IC3F_D32_N6 (14)
#define CCMR2_IC3F_D32_N8 (15)
#define CCMR2_IC3PSC_D1 (00)
#define CCMR2_IC3PSC_D2 (01)
#define CCMR2_IC3PSC_D4 (10)
#define CCMR2_IC3PSC_D8 (11)

#define CCER_CC4NP (1)
#define CCER_CC4NE (1)
#define CCER_CC4P (1)
#define CCER_CC4E (1)
#define CCER_CC3NP (1)
#define CCER_CC3NE (1)
#define CCER_CC3P (1)
#define CCER_CC3E (1)
#define CCER_CC2NP (1)
#define CCER_CC2NE (1)
#define CCER_CC2P (1)
#define CCER_CC2E (1)
#define CCER_CC1NP (1)
#define CCER_CC1NE (1)
#define CCER_CC1P (1)
#define CCER_CC1E (1)

#define BDTR_MOE (1)
#define BDTR_AOE (1)
#define BDTR_BKP (1)
#define BDTR_BKE (1)
#define BDTR_OSSR (1)
#define BDTR_OSSI (1)
#define BDTR_LOCK_OFF (0)
#define BDTR_LOCK_LEVEL1 (1)
#define BDTR_LOCK_LEVEL2 (10)
#define BDTR_LOCK_LEVEL3 (11)

#define PMCR1_EN (1)
#define PMCR1_RELA_EN (1)
#define PMCR1N_RELA_EN (1)
#define PMCR2_EN (1)
#define PMCR2_RELA_EN (1)
#define PMCR2N_RELA_EN (1)
#define PMCR3_EN (1)
#define PMCR3_RELA_EN (1)
#define PMCR3N_RELA_EN (1)
#define PMCR4_EN (1)
#define PMCR4_RELA_EN (1)
#define PMCR4N_RELA_EN (1)

#define PWMT_PUE_CHO1 (1 << 0)
#define PWMT_PUE_CHO2 (1 << 1)
#define PWMT_PUE_CHO3 (1 << 2)
#define PWMT_PUE_CHO4 (1 << 3)
#define PWMT_PUE_CHO1N (1 << 4)
#define PWMT_PUE_CHO2N (1 << 5)
#define PWMT_PUE_CHO3N (1 << 6)
#define PWMT_PUE_CHO4N (1 << 7)

#endif /* end __PWMT__ */

#endif /* end __MODULE_BIT__ */

#define ALG_BASE    0x40041000
#define AES_BASE    0x40041100
#define AESDIOR               (AES_BASE + 0x0000)

#define AES_KEY0              (AES_BASE + 0x0004)
#define AES_KEY1              (AES_BASE + 0x0008)
#define AES_KEY2              (AES_BASE + 0x000c)
#define AES_KEY3              (AES_BASE + 0x0010)
#define AES_KEY4              (AES_BASE + 0x0014)
#define AES_KEY5              (AES_BASE + 0x0018)
#define AES_KEY6              (AES_BASE + 0x001c)
#define AES_KEY7              (AES_BASE + 0x0020)

#define AES_CSR               (AES_BASE + 0x0024)

#define AES_IV0               (AES_BASE + 0x002c)
#define AES_IV1               (AES_BASE + 0x0030)
#define AES_IV2               (AES_BASE + 0x0034)
#define AES_IV3               (AES_BASE + 0x0038)

#define AES_CNT0               (AES_BASE + 0x002c)
#define AES_CNT1               (AES_BASE + 0x0030)
#define AES_CNT2               (AES_BASE + 0x0034)
#define AES_CNT3               (AES_BASE + 0x0038)

#define AES_R4                (AES_BASE + 0x003c)
#define AES_NONCE0            (AES_BASE + 0x0040)
#define AES_NONCE1            (AES_BASE + 0x0044)
#define AES_NONCE2            (AES_BASE + 0x0048)
#define AES_NONCE3            (AES_BASE + 0x004c)

#define AES_ALEN0             (AES_BASE + 0x0050)
#define AES_ALEN1             (AES_BASE + 0x0054)

#define AES_MLEN0             (AES_BASE + 0x0058)
#define AES_MLEN1             (AES_BASE + 0x005c)

#define AES_IVLEN             (AES_BASE + 0x0060)
#define AESIE                           0x00000080
#define AESRST                          0x00000040
#define AESECB                          0x00000000
#define AESCBC                          0x00000200
#define AESCFB                          0x00000400
#define AESOFB                          0x00000600
#define AESCTR                          0x00000800
#define AESCCM                          0x00000a00
#define AESGCM                          0x00000c00
#define AESWRAP                         0x00000e00
#define AESCCM_START                    0x00000100
#define AESGCM_START                    0x00001000
#define AESGCM_INIT_JUMP                0x00002000
#define AESNEW_KEY                      0x00000000
#define AESDONE                         0x00000010

#define AESLAST                         0x08000000
#define AES_CO1                         0x00000000
#define AES_CO8                         0x01000000
#define AES_CO16                        0x02000000
#define AES_CO32                        0x03000000
#define AES_CO64                        0x04000000
#define AES_CO128                       0x05000000

#define AESBUSY                         0x00000008
#define AESKEYMODE00                    0x00000000
#define AESKEYMODE01                    0x00000002
#define AESKEYMODE10                    0x00000004
#define AESCMODE                        0x00000001

#define AESDPA_EN_0                     0x00008000
#define AESDPA_EN_1                     0x00004000
#define AESDPA_EN_2                     0x0000c000
#define AES_CLK_DIV_DPA         				0x80000000

    /***definition of enum and struct********************************************************/

/**
* @brief ADC
*/
typedef struct
{
	/*!< ADC base address 0x40020000*/
	__IO uint32_t ADC_ISR;       /*!< ADC interrupt and status register. Address offset: 0x00*/
	__IO uint32_t ADC_IER;       /*!< ADC interrupt enable register.     Address offset: 0x04*/
	__IO uint32_t ADC_CR;        /*!< ADC control register.              Address offset: 0x08*/
	__IO uint32_t ADC_CFGR1;     /*!< ADC configuration register1.       Address offset: 0x0C*/
	__IO uint32_t ADC_CFGR2;     /*!< ADC configiration register2.       Address offset: 0x10*/
	__IO uint32_t ADC_SMPR;      /*!< ADC sample time register.          Address offset: 0x14*/
	__IO uint32_t ADC_WDG;       /*!< ADC watchdog register.             Address offset: 0x18*/
	__IO uint32_t ADC_TR;        /*!< ADC watchdog threshold register.   Address offset: 0x1C*/

			 uint32_t RESERVED1[3];  /*!< RESERVED1 */                                 
	__IO uint32_t ADC_CHSELR1;   /*!< ADC channel seclection register1.  Address offset: 0x2C*/
	__IO uint32_t ADC_CHSELR2;   /*!< ADC channel seclection register2.  Address offset: 0x30*/
			 uint32_t RESERVED2[6];  /*!< RESERVED2.                         Address offset: 0x34*/                                      

	__IO uint32_t ADC_FIFOR;     /*!< ADC FIFO register.                 Address offset: 0x4C*/
	__IO uint32_t RESERVED3;     /*!< RESERVED3.                         Address offset: 0x50*/   
	__IO uint32_t ADC_ISR2;      /*!< ADC interrupt and status registers.Address offset: 0x54*/
	__IO uint32_t ADC_DGATR;     /*!< ADC data sample register.          Address offset: 0x58*/
	__IO uint32_t ADC_DBUFR;     /*!< ADC data buffer register.          Address offset: 0x5C*/
	__IO uint32_t ADC_FIFOTOR;   /*!< ADC FIFO timeout register.         Address offset: 0x60*/
			 uint32_t RESERVED4[7];  /*!< RESERVED4.                         Address offset: 0x64*/  

	union
	{
		__IO uint32_t ADC_DET3;  /*!< ADC data for test 3.               Address offset: 0x80 */
		struct
		{
			__IO uint16_t CHANEL6;
			__IO uint16_t CHANEL7;
		} DET3;
	};
	union
	{
		__IO uint32_t ADC_DET2; /*!< ADC data for test 2.                Address offset: 0x84*/
		struct
		{
			__IO uint16_t CHANEL4;
			__IO uint16_t CHANEL5;
		} DET2;
	};
	union
	{
			__IO uint32_t ADC_DET1; /*!< ADC data for test 1.                Address offset: 0x88*/
			struct
			{
					__IO uint16_t CHANEL2;
					__IO uint16_t CHANEL3;
			} DET1;
	};
	union
	{
			__IO uint32_t ADC_DET0; /*!< ADC data for test 0.                Address offset: 0x8c*/
			struct
			{
					__IO uint16_t CHANEL0;
					__IO uint16_t CHANEL1;
			} DET0;
	};

	union
	{
			__IO uint32_t ADC_DET7; /*!< ADC data for test 7.                Address offset: 0x90*/
			struct
			{
					__IO uint16_t CHANEL14;
					__IO uint16_t CHANEL15;
			} DET7;
	};
	union
	{
			__IO uint32_t ADC_DET6; /*!< ADC data for test 6.                Address offset: 0x94*/
			struct
			{
					__IO uint16_t CHANEL12;
					__IO uint16_t CHANEL13;
			} DET6;
	};
	union
	{
			__IO uint32_t ADC_DET5; /*!< ADC data for test 5.                Address offset: 0x98*/
			struct
			{
					__IO uint16_t CHANEL10;
					__IO uint16_t CHANEL11;
			} DET5;
	};
	union
	{
			__IO uint32_t ADC_DET4; /*!< ADC data for test 4.                Address offset: 0x9c*/
			struct
			{
					__IO uint16_t CHANEL8;
					__IO uint16_t CHANEL9;
			} DET4;
	};

	union
	{
			__IO uint32_t ADC_DET8; /*!< ADC data for test 8.                Address offset: 0xA0*/
			struct
			{
					__IO uint16_t CHANEL16;
					__IO uint16_t RESERVED5;
			} DET8;
	};
	__IO uint32_t ADC_CHSELR3; /*!< ADC channel seclection register3.  Address offset: 0xA4*/
} ADC_TypeDef;

/**
* @brief  CACHE register definition
*/

/* CACHE register definition */
typedef struct
{
	__IO uint32_t CACHE_CCR;        /*!< CACHE control register.                             Address offset: 0x000*/
	__IO uint32_t CACHE_CLCR;       /*!< CACHE cache line command control register.          Address offset: 0x004*/
	__IO uint32_t CACHE_CSAR;       /*!< CACHE address query register register.              Address offset: 0x008*/
	__IO uint32_t CACHE_CCVR;       /*!< CACHE read/write data register.                     Address offset: 0x00C*/
			 uint32_t RESERVED1[4];     /*!< RESERVED1.                                          Address offset: 0x010*/
	__IO uint32_t CACHE_CACR;       /*!< CACHE primary address block access register.        Address offset: 0x020*/
	__IO uint32_t CACHE_CSACR;      /*!< CACHE sub-address block access control register.    Address offset: 0x024*/
			 uint32_t RESERVED2[6];     /*!< RESERVED2.                                          Address offset: 0x028*/
	__IO uint32_t CACHE_CR6S0HA;    /*!< CACHE segment-6 subarea-0 address cap register.     Address offset: 0x040*/
	__IO uint32_t CACHE_CR6S1HA;    /*!< CACHE segment-6 subarea-1 address cap register.     Address offset: 0x044*/
	__IO uint32_t CACHE_CR6S2HA;    /*!< CACHE segment-6 subarea-2 address cap register.     Address offset: 0x048*/
	__IO uint32_t CACHE_CR6S3HA;    /*!< CACHE segment-6 subarea-3 address cap register.     Address offset: 0x04C*/
	__IO uint32_t CACHE_CR6S0LA;    /*!< CACHE segment-6 subarea-0 address lower register.   Address offset: 0x050*/
	__IO uint32_t CACHE_CR6S1LA;    /*!< CACHE segment-6 subarea-1 address lower register.   Address offset: 0x054*/
	__IO uint32_t CACHE_CR6S2LA;    /*!< CACHE segment-6 subarea-3 address lower register.   Address offset: 0x058*/
	__IO uint32_t CACHE_CR6S3LA;    /*!< CACHE segment-6 subarea-4 address lower register.   Address offset: 0x05C*/
	__IO uint32_t CACHE_CR7S0HA;    /*!< CACHE segment-7 subarea-0 address cap register.     Address offset: 0x060*/
	__IO uint32_t CACHE_CR7S1HA;    /*!< CACHE segment-7 subarea-1 address cap register.     Address offset: 0x064*/ 
	__IO uint32_t CACHE_CR7S2HA;    /*!< CACHE segment-7 subarea-2 address cap register.     Address offset: 0x068*/
	__IO uint32_t CACHE_CR7S3HA;    /*!< CACHE segment-7 subarea-3 address cap register.     Address offset: 0x06C*/
	__IO uint32_t CACHE_CR7S0LA;    /*!< CACHE segment-7 subarea-0 address lower register.   Address offset: 0x070*/
	__IO uint32_t CACHE_CR7S1LA;    /*!< CACHE segment-7 subarea-1 address lower register.   Address offset: 0x074*/
	__IO uint32_t CACHE_CR7S2LA;    /*!< CACHE segment-7 subarea-3 address lower register.   Address offset: 0x078*/
	__IO uint32_t CACHE_CR7S3LA;    /*!< CACHE segment-7 subarea-4 address lower register.   Address offset: 0x07C*/
	__IO uint32_t CACHE_CR2S0HA;    /*!< CACHE segment-2 subarea-0 address cap register.     Address offset: 0x080*/
	__IO uint32_t CACHE_CR2S1HA;    /*!< CACHE segment-2 subarea-1 address cap register.     Address offset: 0x084*/
	__IO uint32_t CACHE_CR2S2HA;    /*!< CACHE segment-2 subarea-2 address cap register.     Address offset: 0x088*/
	__IO uint32_t CACHE_CR2S3HA;    /*!< CACHE segment-2 subarea-3 address cap register.     Address offset: 0x08C*/
	__IO uint32_t CACHE_CR2S0LA;    /*!< CACHE segment-2 subarea-0 address lower register.   Address offset: 0x090*/
	__IO uint32_t CACHE_CR2S1LA;    /*!< CACHE segment-2 subarea-1 address lower register.   Address offset: 0x094*/
	__IO uint32_t CACHE_CR2S2LA;    /*!< CACHE segment-2 subarea-3 address lower register.   Address offset: 0x098*/
	__IO uint32_t CACHE_CR2S3LA;    /*!< CACHE segment-2 subarea-4 address lower register.   Address offset: 0x09C*/
			 uint32_t RESERVED3[20];    /*!< RESERVED3.                                          Address offset: 0x100*/
	__IO uint32_t CACHE_CPEA;       /*!< CACHE page clear address register.                  Address offset: 0x180*/ 
	__IO uint32_t CACHE_CPES;       /*!< CACHE page clear size register.                     Address offset: 0x184*/
	__IO uint32_t CACHE_CCG;        /*!< CACHE clock gate register.                          Address offset: 0x188*/
} CACHE_TypeDef;

/**
* @brief  CCM register definition
*/
typedef struct
{
	/*!< CCM base address: 0x40001000. */
	__IO uint16_t RESERVED0;        /*!< CCM FD configuration.                        Address offset: 0x00*/
	__IO uint16_t CCR;              /*!< CCM chip configuration register.             Address offset: 0x02*/
	__IO uint16_t CIR;              /*!< CCM chip identification register.            Address offset: 0x04*/
	__IO uint16_t PHYPA;            /*!< CCM PHY parameter configuration register.    Address offset: 0x06*/  
	__IO uint16_t RESERVED1;        /*!< RESERVED1.                                   Address offset: 0x08*/
	__IO uint16_t CTR;              /*!< CCM chip test register.                      Address offset: 0x0A*/
	__IO uint32_t RESERVED2;        /*!< RESERVED2.                                   Address offset: 0x0C*/

	__IO uint32_t PCFG12;           /*!< CCM PMU1/2 configuration register.           Address offset: 0x10*/
	__IO uint32_t PCFG3;            /*!< CCM PMU3 configuration register.             Address offset: 0x14*/
	__IO uint32_t RESERVED3;        /*!< RESERVED3.                                  Address offset: 0x18*/
	__IO uint32_t RTCCFG3;          /*!< CCM RTC3 configuration register.             Address offset: 0x1C*/

	__IO uint32_t RTCSR;            /*!< CCM RTC status register.                     Address offset: 0x20*/
			 uint32_t RESERVED4;        /*!< RESERVED4.                                   Address offset: 0x24*/
	__IO uint32_t OTG_PHY_CTRL;     /*!< CCM OTG_PHY_CTRL register.                   Address offset: 0x28*/
	__IO uint32_t RESERVED5[4];     /*!< RESERVED5[4].                                Address offset: 0x2C~0x38*/
	__IO uint32_t SSICFGR;          /*!< CCM SSICFGR register.                        Address offset: 0x3C */
} CCM_TypeDef;

/**
* @brief  CRC register definition
*/
typedef struct
{
	/*!< CRC base address 0x40021000*/
	__IO uint32_t CR;                  /*!< CRC control register.              Address offset: 0x00*/
	__IO uint32_t RES;                 /*!< CRC result register.               Address offser: 0x04*/
	__IO uint32_t INIT_DATA;           /*!< CRC initial data register.         Address offser: 0x08*/
	__IO uint32_t DATA_IN;             /*!< CRC data in register.              Address offser: 0x0C*/
	__IO uint32_t DMAC_DATA_IN;        /*!< CRC DMAC data in register.         Address offser: 0x10*/
} CRC_TypeDef;

/**
* @brief CLOCK and POWER
*/
typedef struct
{
	/*!< CPM base address: 0x40004000. */
	__IO uint32_t SLPCFGR;        /*!< CPM sleep configuration register.                 Address offset: 0x00*/
	__IO uint32_t SLPCR;          /*!< CPM sleep control register.                       Address offset: 0x04*/
	__IO uint32_t SCDIVR;         /*!< CPM system clock divider register.                Address offset: 0x08*/
	__IO uint32_t PCDIVR1;        /*!< CPM peripheral clcok divider register1.           Address offset: 0x0C*/
	__IO uint32_t PCDIVR2;        /*!< CPM peripheral clcok divider register2.           Address offset: 0x10*/

	__IO uint32_t RESERVED;       /*!< RESERVED.                                         Address offset: 0x14*/
	__IO uint32_t CDIVUPDR;       /*!< CPM clcok divider update register.                Address offset: 0x18*/
	__IO uint32_t CDIVENR;        /*!< CPM clcok divider enable register.                Address offset: 0x1C*/

	__IO uint32_t OCSR;           /*!< CPM crystal oscillator control register.          Address offset: 0x20*/
	__IO uint32_t CSWCFGR;        /*!< CPM clock switching configuration register.       Address offset: 0x24*/
	__IO uint32_t CTICKR;         /*!< CPM core tick register.                           Address offset: 0x28*/
	__IO uint32_t CHIPCFGR;       /*!< CPM chip control register.                        Address offset: 0x2C*/

	__IO uint32_t PWRCR;          /*!< CPM power control register.                       Address offset: 0x30*/
	__IO uint32_t SLPCNTR;        /*!< CPM sleep count register.                         Address offset: 0x34*/
	__IO uint32_t WKPCNTR;        /*!< CPM wakeup count register.                        Address offset: 0x38*/
	__IO uint32_t MULTICGTCR;     /*!< CPM multiple clock gate register.                 Address offset: 0x3C*/

	__IO uint32_t SYSCGTCR;       /*!< CPM system clock gate register.                   Address offset: 0x40*/
	__IO uint32_t AHB3CGTCR;      /*!< CPM AHB3 clock gate register.                     Address offset: 0x44*/
	__IO uint32_t ARITHCGTCR;     /*!< CPM algorithm clock gate register.                Address offset: 0x48*/
	__IO uint32_t IPSCGTCR;       /*!< CPM IPC clock gate register.                      Address offset: 0x4C*/

	__IO uint32_t VCCGTRIMR;      /*!< CPM VCC check register.                           Address offset: 0x50*/
	__IO uint32_t VCCLTRIMR;      /*!< CPM LVDT register.                                Address offset: 0x54*/
	__IO uint32_t VCCVTRIMR;      /*!< CPM VCC reference voltage register.               Address offset: 0x58*/
	__IO uint32_t VCCCTMR;        /*!< CPM core test mode register.                      Address offset: 0x5C*/

	__IO uint32_t O8MTRIMR;       /*!< CPM OSC-8M check register.                        Address offset: 0x60*/
	__IO uint32_t RESERVED2;      /*!< RESERVED2.                                        Address offset: 0x64*/
	__IO uint32_t O400MTRIMR;     /*!< CPM OSC-120M check register.                      Address offset: 0x68*/
	__IO uint32_t CARDTRIMR;      /*!< CPM card ldo check register.                      Address offset: 0x6C*/

	__IO uint32_t OSCLSTIMER;     /*!< CPM OSCL stable time register.                    Address offset: 0x70*/
	__IO uint32_t OSCHSTIMER;     /*!< CPM OSCH stable time register.                    Address offset: 0x74*/
	__IO uint32_t OSCESTIMER;     /*!< CPM OSCE stable time register.                    Address offset: 0x78*/
	__IO uint32_t PWRSR;          /*!< CPM power state register.                         Address offset: 0x7C*/

	__IO uint32_t EPORTSLPCFGR;   /*!< CPM EPORTSLPCFGR register.                        Address offset: 0x80*/ 
	__IO uint32_t EPORTCGTR;      /*!< CPM EPORTCGTR register.                           Address offset: 0x84*/
	__IO uint32_t EPORTRSTCR;     /*!< CPM EPORTRSTCR register.                          Address offset: 0x88*/ 
	__IO uint32_t RESERVED3;      /*!< RESERVED3.                                        Address offset: 0x8C*/

	__IO uint32_t PADWKINTCR;     /*!< CPM pin wakeup interrupt register.                Address offset: 0x90*/
	__IO uint32_t WKPFILTCNTR;    /*!< CPM wakeup filtering register.                    Address offset: 0x94*/
	__IO uint32_t RESERVED4;      /*!< RESERVED4.                                        Address offset: 0x98*/
	__IO uint32_t RESERVED5;      /*!< RESERVED5.                                        Address offset: 0x9C*/

	__IO uint32_t MPDSLPCR;       /**< A0 memory power down sleep control register                           */
	__IO uint32_t RESERVED6[2];   /**< RESERVED2[2]. 0xA4 0xA8                                               */
	__IO uint32_t MULTIRSTCR;     /*!< CPM memory power-down sleep control register.     Address offset: 0xAC*/

	__IO uint32_t SYSRSTCR;       /*!< CPM system reset control register.                Address offset: 0xB0*/
	__IO uint32_t AHB3RSTCR;      /*!< CPM AHB3 reset control register.                  Address offset: 0xB4*/
	__IO uint32_t ARITHRSTTCR;    /*!< CPM algorithm reset register.                     Address offset: 0xB8*/
	__IO uint32_t IPRSTCR;        /*!< CPM IPS reset control register.                   Address offset: 0xBC*/
	
	__IO uint32_t SLPCFGR2;       /*!< CPM sleep control register.                       Address offset: 0xC0*/
	__IO uint32_t RESERVED7[3];   /*!< RESERVED3[3].                                     Address offset: C4 C8 CC*/

	__IO uint32_t PDNCNTR;        /*!< CPM power down counter register                   Address offset: 0xD0*/
	__IO uint32_t PONCNTR;        /*!< CPM power on counter register                     Address offset: 0xD4*/
	__IO uint32_t PCDIVR4;        /*!< CPM PCDIVR4D8  register                           Address offset: 0xD8*/
	__IO uint32_t RESERVED8;      /*!< RESERVED8                                         Address offset: 0xDC*/
	__IO uint32_t RESERVED9;      /*!< RESERVED9                                         Address offset: 0xE0*/
	__IO uint32_t RESERVED10;     /*!< RESERVED10                                        Address offset: 0xE4*/

} CPM_TypeDef;

/**
* @brief DMA register definition
*
*/
typedef struct
{
	/*!< DMA1 base address: 0x40046000. */
	/*!< DMA2 base address: 0x40047000. */
	/*!< DMA1 channel-0 address: 0x40046000+0x00.  */
	/*!< DMA1 channel-1 address: 0x40046000+0x58.  */
	/*!< DMA1 channel-2 address: 0x40046000+0xB0.  */
	/*!< DMA1 channel-3 address: 0x40046000+0x108. */
	/*!< DMA2 channel-0 address: 0x40047000+0x00.  */
	/*!< DMA2 channel-1 address: 0x40047000+0x58.  */
	/*!< DMA2 channel-2 address: 0x40047000+0xB0.  */
	/*!< DMA2 channel-3 address: 0x40047000+0x108. */
	__IO uint32_t SRCADDR;       /*!< DMA source low address register.           Address offset: 0x00*/
	__IO uint32_t RESERVED0;     /*!< RESERVED0.                                 Address offset: 0x04*/
	__IO uint32_t DSTADDR;       /*!< DMA destination low address register.      Address offset: 0x08*/
	__IO uint32_t RESERVED1;     /*!< RESERVED1.                                 Address offset: 0x0C*/
	__IO uint32_t LLI;           /*!< DMA linked list low address register.      Address offset: 0x10*/
	__IO uint32_t RESERVED2;     /*!< RESERVED2.                                 Address offset: 0x14*/
	__IO uint32_t CTRL;          /*!< DMA control low address register.          Address offset: 0x18*/
	__IO uint32_t CTRL_HIGH;     /*!< DMA control high address register.         Address offset: 0x1C*/
	__I uint32_t RESERVED3[8];   /*!< RESERVED3  20 24 28 2C 30 34 38 3C         Address offset: 0x20*/
	__IO uint32_t CONFIG;        /*!< DMA configuration low address register.    Address offset: 0x40*/
	__IO uint32_t CONFIG_HIGH;   /*!< DMA configuration high address register.   Address offset: 0x44*/
	__I uint32_t RESERVED4[4];   /*!< RESERVED4  48 4C 50 54                     Address offset: 0x48*/
} DMAC_ChannelTypeDef;

/**
* @brief DMA MIN ADDR register definition
*
*/
typedef struct
{
	__IO uint32_t SARADDR;
	__IO uint32_t DSTADDR;
} DMAC_MINADDRTypeDef;

/**
* @brief DMAC register definition
*
*/
typedef struct
{
	DMAC_ChannelTypeDef CH[4];   /**< 0x0000---> 0x015C */

	__IO uint32_t RESERVED0[88]; /**< 0x0160---> 0x02BC */
	__IO uint32_t RAWTFR;        /**< 0x02C0 raw status for intTfr interrupt */
	__IO uint32_t RESERVED1;
	__IO uint32_t RAWBLOCK;      /**< 0x02C8 raw status for intBlock interrupt */
	__IO uint32_t RESERVED2;
	__IO uint32_t RAWSRCTRAN;    /**< 0x02D0 raw status for intScTran interrupt */
	__IO uint32_t RESERVED3;
	__IO uint32_t RAWDETTRAN;    /**< 0x02D8 raw status for intDestTran interrupt */
	__IO uint32_t RESERVED4;
	__IO uint32_t RAWERR;        /**< 0x02EO raw status for intErr interrupt */
	__IO uint32_t RESERVED5;
	__IO uint32_t STATTFR;       /**< 0x02E8  status for intTfr interrupt */
	__IO uint32_t RESERVED6;
	__IO uint32_t STATBLOCK;     /**< 0x02F0  status for intBlock interrupt */
	__IO uint32_t RESERVED7;
	__IO uint32_t STATSRC;       /**< 0x02F8  status for intScTran interrupt */
	__IO uint32_t RESERVED8;
	__IO uint32_t STATDST;       /**< 0x0300  status for intDestTran interrupt */
	__IO uint32_t RESERVED9;
	__IO uint32_t ERR;           /**< 0x0308  status for intErr interrupt */
	__IO uint32_t RESERVED10;
	__IO uint32_t MASKTFR;       /**< 0x0310 mask for intTfr interrupt */
	__IO uint32_t RESERVED11;
	__IO uint32_t MASKBLOCK;     /**< 0x0318 mask for intBlock interrupt */
	__IO uint32_t RESERVED12;
	__IO uint32_t MASKSRC;       /**< 0x0320 mask for intScTran interrupt */
	__IO uint32_t RESERVED13;
	__IO uint32_t MASKDST;       /**< 0x0328 mask for intDestTran interrupt */
	__IO uint32_t RESERVED14;
	__IO uint32_t MASKERR;       /**< 0x0330 mask for intErr interrupt */
	__IO uint32_t RESERVED15;
	__IO uint32_t CLRTFR;        /**< 0x0338 clear for intTfr interrupt */
	__IO uint32_t RESERVED16;
	__IO uint32_t CLRBLOCK;      /**< 0x0340 clear for intBlock interrupt */
	__IO uint32_t RESERVED17;
	__IO uint32_t CLRSRC;        /**< 0x0348 clear for intScTran interrupt */
	__IO uint32_t RESERVED18;
	__IO uint32_t CLRDST;        /**< 0x0350 clear for intDestTran interrupt */
	__IO uint32_t RESERVED19;
	__IO uint32_t CLRERR;        /**< 0x0358 clear for intErr interrupt */
	__IO uint32_t RESERVED20;
	__IO uint32_t STATUSINT;     /**< 0x0360 status for each interrupt type */
	__IO uint32_t RESERVED21;
	__IO uint32_t SRCREQ;        /**< 0x0368 transacion request */
	__IO uint32_t RESERVED22;
	__IO uint32_t DESTREQ;       /**< 0x0370 transacion request */
	__IO uint32_t RESERVED23;
	__IO uint32_t SINGLESRC;     /**< 0x0378 transacion request */
	__IO uint32_t RESERVED24;
	__IO uint32_t SINGLEDST;     /**< 0x0380 transacion request */
	__IO uint32_t RESERVED25;
	__IO uint32_t LASTSRC;       /**< 0x0388 transacion request */
	__IO uint32_t RESERVED26;
	__IO uint32_t LASTDST;       /**< 0x0390 transacion request */
	__IO uint32_t RESERVED27;
	__IO uint32_t CONFIG;        /**< 0x0398 confuration  */
	__IO uint32_t RESERVED28;
	__IO uint32_t CHEN;          /**< 0x03A0 cannel enable  */
	__IO uint32_t RESERVED29[7]; /**< 0x03A4---> 0x03BC */
	__IO uint32_t RAWMIN;        /**< 0x03C0 raw status for intMIN interrupt */
	__IO uint32_t RESERVED30;
	__IO uint32_t MASKMIN;       /**< 0x03C8 mask status for intMIN interrupt */
	__IO uint32_t RESERVED31;
	__IO uint32_t CLRMIN;        /**< 0x03D0 clear status for intMIN interrupt */
	__IO uint32_t RESERVED32;

	DMAC_MINADDRTypeDef MIN_CH[4]; /**< 0x03D8---> 0x03F4 */
} DMAC_TypeDef;


typedef struct _DMA_CONTROL_REG
{
	/*!< DMA1 base address: 0x40046000. */
	__IO uint32_t DMA_RAWTFR;        /*!< DMA raw status register.                          Address offset: 0x00/0x2C0*/
			 uint32_t RESERVED1;         /*!< RESERVED1.                                        Address offset: 0x04/0x2C4*/
	__IO uint32_t DMA_RAWBLOCK;      /*!< DMA raw block register.                           Address offset: 0x08/0x2C8*/
			 uint32_t RESERVED2;         /*!< RESERVED2.                                        Address offset: 0x0C/0x2CC*/
	__IO uint32_t DMA_RAWSRCTRAN;    /*!< DMA raw source transfer register.                 Address offset: 0x10/0x2D0*/
			 uint32_t RESERVED3;         /*!< RESERVED3.                                        Address offset: 0x14/0x2D4*/
	__IO uint32_t DMA_RAWDSTTRAN;    /*!< DMA raw destination transfer register.            Address offset: 0x18/0x2D8*/
			 uint32_t RESERVED4;         /*!< RESERVED4.                                        Address offset: 0x1C/0x2DC*/
	__IO uint32_t DMA_RAWERR;        /*!< DMA raw error register.                           Address offset: 0x20/0x2E0*/
			 uint32_t RESERVED5;         /*!< RESERVED5.                                        Address offset: 0x24/0x2E4*/
	__IO uint32_t DMA_STATTFR;       /*!< DMA status register.                              Address offset: 0x28/0x2E8*/
			 uint32_t RESERVED6;         /*!< RESERVED6.                                        Address offset: 0x2C/0x2EC*/
	__IO uint32_t DMA_STATBLOCK;     /*!< DMA status block register.                        Address offset: 0x30/0x2F0*/
			 uint32_t RESERVED7;         /*!< RESERVED7.                                        Address offset: 0x34/0x2F4*/
	__IO uint32_t DMA_STATSRC;       /*!< DMA status source register.                       Address offset: 0x38/0x2F8*/
			 uint32_t RESERVED8;         /*!< RESERVED8.                                        Address offset: 0x3C/0x2FC*/
	__IO uint32_t DMA_STATDST;       /*!< DMA status destination register.                  Address offset: 0x40/0x300*/
			 uint32_t RESERVED9;         /*!< RESERVED9.                                        Address offset: 0x44/0x304*/
	__IO uint32_t DMA_STATERR;       /*!< DMA status error register.                        Address offset: 0x48/0x308*/
			 uint32_t RESERVED10;        /*!< RESERVED10.                                       Address offset: 0x4C/0x30C*/

	__IO uint32_t DMA_MASKTFR;        /*!< DMA mask status register.                         Address offset: 0x50/0x310*/
			 uint32_t RESERVED11;         /*!< RESERVED11.                                       Address offset: 0x54/0x314*/
	__IO uint32_t DMA_MASKBLOCK;      /*!< DMA mask block register.                          Address offset: 0x58/0x318*/
			 uint32_t RESERVED12;         /*!< RESERVED12.                                       Address offset: 0x5C/0x31C*/
	__IO uint32_t DMA_MASKSRC;        /*!< DMA mask source register.                         Address offset: 0x60/0x320*/
			 uint32_t RESERVED13;         /*!< RESERVED13.                                       Address offset: 0x64/0x324*/
	__IO uint32_t DMA_MASKDST;        /*!< DMA mask destination register.                    Address offset: 0x68/0x328*/
			 uint32_t RESERVED14;         /*!< RESERVED14.                                       Address offset: 0x6C/0x32C*/
	__IO uint32_t DMA_MASKERR;        /*!< DMA mask error register.                          Address offset: 0x70/0x330*/
			 uint32_t RESERVED15;         /*!< RESERVED15.                                       Address offset: 0x74/0x334*/
	__IO uint32_t DMA_CLRTFR;         /*!< DMA clear status register.                        Address offset: 0x78/0x338*/
			 uint32_t RESERVED16;         /*!< RESERVED16.                                       Address offset: 0x7C/0x33C*/
	__IO uint32_t DMA_CLRBLOCK;       /*!< DMA clear block register.                         Address offset: 0x80/0x340*/
			 uint32_t RESERVED17;         /*!< RESERVED17.                                       Address offset: 0x84/0x344*/
	__IO uint32_t DMA_CLRSRC;         /*!< DMA clear source register.                        Address offset: 0x88/0x348*/
			 uint32_t RESERVED18;         /*!< RESERVED18.                                       Address offset: 0x8C/0x34C*/
	__IO uint32_t DMA_CLRDST;         /*!< DMA clear destination register.                   Address offset: 0x90/0x350*/
			 uint32_t RESERVED19;         /*!< RESERVED19.                                       Address offset: 0x94/0x354*/
	__IO uint32_t DMA_CLRERR;         /*!< DMA clear error register.                         Address offset: 0x98/0x358*/
			 uint32_t RESERVED20;         /*!< RESERVED20.                                       Address offset: 0x9C/0x35C*/

	__IO uint32_t DMA_STATUSINT;     /*!< DMA status merage register.                       Address offset: 0x100/0x360*/
			 uint32_t RESERVED21;        /*!< RESERVED21.                                       Address offset: 0x104/0x364*/
	__IO uint32_t DMA_SRCREQ;        /*!< DMA source transfer request register.             Address offset: 0x108/0x368*/
			 uint32_t RESERVED22;        /*!< RESERVED22.                                       Address offset: 0x10C/0x36C*/
	__IO uint32_t DMA_DSTREQ;        /*!< DMA destination transfer request register.        Address offset: 0x110/0x370*/
			 uint32_t RESERVED23;        /*!< RESERVED23.                                       Address offset: 0x114/0x374*/
	__IO uint32_t DMA_SINGLESRC;     /*!< DMA single transfer request source register.      Address offset: 0x118/0x378*/
			 uint32_t RESERVED24;        /*!< RESERVED24.                                       Address offset: 0x11c/0x37c*/
	__IO uint32_t DMA_SINGLEDST;     /*!< DMA single transfer request destination register. Address offset: 0x120/0x380*/
			 uint32_t RESERVED25;        /*!< RESERVED25.                                       Address offset: 0x124/0x384*/
	__IO uint32_t DMA_LASTSRC;       /*!< DMA last transfer request source register.        Address offset: 0x128/0x388*/
			 uint32_t RESERVED26;        /*!< RESERVED26.                                       Address offset: 0x12C/0x38C*/
	__IO uint32_t DMA_LASTDST;       /*!< DMA last transfer request destination register.   Address offset: 0x130/0x390*/
			 uint32_t RESERVED27;        /*!< RESERVED27.                                       Address offset: 0x134/0x394*/
	__IO uint32_t DMA_CONFIG;        /*!< DMA configuration register.                       Address offset: 0x138/0x398*/
			 uint32_t RESERVED28;        /*!< RESERVED28.                                       Address offset: 0x13C/0x39C*/
	__IO uint32_t DMA_CHEN;          /*!< DMA channel enable register.                      Address offset: 0x140/0x3A0*/

}DMA_CONTROL_REG;

/**
* @brief EMDAC register definition
*/
typedef struct
{
	/*!< EDMA channel-1 base address: 0x4000a000+0x40.*/
	__IO uint32_t CR;          /*!< EDMA channel control register.                    Address offset: 0x00/0x40*/
	__IO uint32_t CSR;         /*!< EDMA status register.                             Address offset: 0x04/0x44*/
	__IO uint32_t RBAR;        /*!< EDMA channel read buffer address register.        Address offset: 0x08/0x48*/
	__IO uint32_t WBAR;        /*!< EDMA channel write buffer address register.       Address offset: 0x0C/0x4C*/
	__IO uint32_t MINSUMR;     /*!< EDMA secondary transfer summary register.         Address offset: 0x10/0x50*/
	__IO uint32_t MINCNTR;     /*!< EDMA secondary transfer count register.           Address offset: 0x14/0x54*/
	__IO uint32_t MAJSUMR;     /*!< EDMA major transfer summary register.             Address offset: 0x18/0x58*/
	__IO uint32_t MAJCNTR;     /*!< EDMA major transfer count register.               Address offset: 0x1C/0x5C*/
	__IO uint32_t SPAR;        /*!< EDMA special periphial register.                  Address offset: 0x20/0x60*/
	__IO uint32_t WBARSTEP;    /*!< EDMA WBARSTEP register.                           Address offset: 0x24/0x64*/
	__IO uint32_t LASTMINSUMR; /*!< EDMA LASTMINSUMR register.                        Address offset: 0x28/0x68*/
} EDMAC_TypeDef;

/**
* @brief  EPORT register definition
*/
typedef struct
{
	/*!< EPORT0 Address: 0x40019000. */
	/*!< EPORT1 Address: 0x4001A000. */
	/*!< EPORT2 Address: 0x40024000. */
	/*!< EPORT4 Address: 0x40027000. */
	/*!< EPORT5 Address: 0x40028000. */
	/*!< EPORT6 Address: 0x40029000. */
	union
	{
			__IO uint16_t EPPAR; /*!< GPIO configuration register.            Address offset: 0x00*/
			struct
			{
					__IO uint8_t EPPAR_L;
					__IO uint8_t EPPAR_H;
			} EPPARHL;
	};

	__IO uint8_t  EPIER;         /*!< GPIO interrupt enable register.         Address offset: 0x02*/
	__IO uint8_t  EPDDR;         /*!< GPIO data direction register.           Address offset: 0x03*/
	__IO uint8_t  EPPDR;         /*!< GPIO pin data register.                 Address offset: 0x04*/
	__IO uint8_t  EPDR;          /*!< GPIO data register.                     Address offset: 0x05*/
	__IO uint8_t  EPPUER;        /*!< GPIO pin pullup enable register.        Address offset: 0x06*/
	__IO uint8_t  EPFR;          /*!< GPIO flag register.                     Address offset: 0x07*/
	__IO uint8_t  EPODER;        /*!< GPIO open drain register.               Address offset: 0x08*/
	__IO uint8_t  EPLPR;         /*!< GPIO levle polarity register.           Address offset: 0x09*/
	
} EPORT_TypeDef;

/**
* @brief OTP register definition
*/
typedef struct
{
	__IO uint32_t OTPCR;      /*!< OTP OTPCR register.       Address offset: 00*/
	__IO uint32_t OTPAPR;     /*!< OTP OTPAPR register.      Address offset: 04*/
	__IO uint32_t OTPSTAT;    /*!< OTP OTPSTAT register.     Address offset: 08*/
	__IO uint32_t OTPINTM;    /*!< OTP OTPINTM register.     Address offset: 0C*/
	__IO uint32_t OTPCMD;     /*!< OTP OTPCMD register.      Address offset: 10*/
	__IO uint32_t OTPTIMBASE; /*!< OTP OTPTIMBASE register.  Address offset: 14*/
	__IO uint32_t OTPTIMCFG;  /*!< OTP OTPTIMCFG register.   Address offset: 18*/
	__IO uint32_t OTPPTIMER;  /*!< OTP OTPPTIMER register.   Address offset: 1C*/
} OTP_TypeDef;

/**
* @brief I2C register definition
*/
typedef struct
{
	/*!< I2C base address: 0x40017000. */
	__IO uint8_t SARH;      /*!< I2C slave high address register.       Address offset: 0x00*/
	__IO uint8_t SARL;      /*!< I2C slave low address register .       Address offset: 0x01*/
	__IO uint8_t CCR;       /*!< I2C control register.                  Address offset: 0x02*/
	__IO uint8_t PR;        /*!< I2C clock Prescale divider register.   Address offset: 0x03*/
	__IO uint8_t SR;        /*!< I2C status register.                   Address offset: 0x04*/
	__IO uint8_t DR;        /*!< I2C slave data register.               Address offset: 0x05*/
	__IO uint8_t SHTR;      /*!< I2C slave keep time register.          Address offset: 0x06*/
	__IO uint8_t SHIR;      /*!< I2C slave high speed flag register.    Address offset: 0x07*/
	__IO uint8_t PCR;       /*!< I2C port control register.             Address offset: 0x08*/
	__IO uint8_t PDR;       /*!< I2C port data register.                Address offset: 0x09*/
	__IO uint8_t DDR;       /*!< I2C port direction register.           Address offset: 0x0A*/
	__IO uint8_t FCTR;      /*!< I2C filter and power test register.    Address offset: 0x0B*/
	__IO uint8_t NSFTVR_10; /*!< I2C filter adjustment 10ns register.   Address offset: 0x0C*/
	__IO uint8_t NSFTVR_50; /*!< I2C filter adjustment 50ns register.   Address offset: 0x0D*/
} I2C_TypeDef;


/**
* @brief  IOCTRL register definition
*/
typedef struct
{
	volatile uint32_t SPICR;     /*!< IOCTRL SPI pin control register.               Address offset: 0x00*/
	volatile uint32_t USICR;     /*!< IOCTRL ISO7816 pin control register.           Address offset: 0x04*/
	volatile uint32_t I2CCR;     /*!< IOCTRL I2C pin control register.               Address offset: 0x08*/
	volatile uint32_t UARTCR;    /*!< IOCTRL UART pin control register.              Address offset: 0x0C*/
	volatile uint32_t GINTLCR;   /*!< IOCTRL GPIO-A[7-0] control register.           Address offset: 0x10*/
	volatile uint32_t GINTHCR;   /*!< IOCTRL GPIO-A[15-8] control register.          Address offset: 0x14*/
	volatile uint32_t RESERVED;  /**< RESERVED 0x18  */
	volatile uint32_t SWAPCR;    /*!< IOCTRL swap pin control register.              Address offset: 0x1C*/
	volatile uint32_t SPIM1CR;   /*!< IOCTRL SPIM1 pin control register.             Address offset: 0x20*/
	volatile uint32_t RESERVED2; /*!< RESERVED2.                                     Address offset: 0x24*/
	volatile uint32_t RESERVED3; /*!< RESERVED3.                                     Address offset: 0x28*/
	volatile uint32_t RESERVED4; /*!< RESERVED4.                                     Address offset: 0x2C*/
	volatile uint32_t RESERVED5; /*!< RESERVED5.                                     Address offset: 0x30*/
	volatile uint32_t RESERVED6; /*!< RESERVED6.                                     Address offset: 0x34*/
	volatile uint32_t WKUPPADCR; /*!< IOCTRL WKUPPADCR register.                     Address offset: 0x38*/
	volatile uint32_t RESERVED7; /*!< RESERVED7.                                     Address offset: 0x3C*/
	volatile uint32_t RESERVED8; /*!< RESERVED8.                                     Address offset: 0x40*/
	volatile uint32_t RESERVED9; /*!< RESERVED9.                                     Address offset: 0x44*/
	volatile uint32_t PSRAMCR1;  /*!< IOCTRL PSRAMCR1 register.                      Address offset: 0x48*/
	volatile uint32_t PSRAMCR2;  /*!< IOCTRL PSRAMCR2 register.                      Address offset: 0x4C*/
	volatile uint32_t PSRAMCR3;  /*!< IOCTRL PSRAMCR3 register.                      Address offset: 0x50*/
	volatile uint32_t EPORT2CR;  /*!< IOCTRL EPORT2CR register.                      Address offset: 0x54*/
	volatile uint32_t RESERVED10;  /*!< RESERVED10.                                  Address offset: 0x58*/
	volatile uint32_t RESERVED11;  /*!< RESERVED11.                                  Address offset: 0x5C*/
	volatile uint32_t EPORT5CR;  /*!< IOCTRL EPORT5CR register.                      Address offset: 0x60*/
	volatile uint32_t EPORT6CR;  /*!< IOCTRL EPORT6CR register.                      Address offset: 0x64*/
	volatile uint32_t EPORT7CR;  /*!< IOCTRL EPORT7CR register.                      Address offset: 0x68*/
	volatile uint32_t SWAPCR2;   /**< IOCTRL SWAPCR2 register.                       Address offset: 0x6C*/
	volatile uint32_t SWAPCR3;   /**< IOCTRL SWAPCR3 register.                       Address offset: 0x70*/
	volatile uint32_t SWAPCR4;   /**< IOCTRL SWAPCR4 register.                       Address offset: 0x74*/
	volatile uint32_t SWAPCR5;   /**< IOCTRL SWAPCR5 register.                       Address offset: 0x78*/
	volatile uint32_t RESERVED12;  /*!< RESERVED12.                                  Address offset: 0x7C*/
	volatile uint32_t RESERVED13;  /*!< RESERVED13.                                  Address offset: 0x80*/
	volatile uint32_t PWMTCR;    /*!< IOCTRL PWMTCR register.                        Address offset: 0x84*/
	volatile uint32_t CANCR;     /*!< IOCTRL CANCR register.                         Address offset: 0x88*/
	volatile uint32_t SPI1CR;    /*!< IOCTRL SPI1CR register.                        Address offset: 0x8C*/
	volatile uint32_t SPI2CR;    /*!< IOCTRL SPI2CR register.                        Address offset: 0x90*/
	volatile uint32_t SPI3CR;    /*!< IOCTRL SPI3CR register.                        Address offset: 0x94*/
	volatile uint32_t WDTCR;     /*!< IOCTRL WDTCR register.                         Address offset: 0x98*/
	volatile uint32_t SWAPCR6;   /*!< IOCTRL SWAPCR6 register.                       Address offset: 0x9C*/
} IOCTRL_TypeDef;

/**
* @brief  LED definition
*/
typedef struct
{
	volatile uint8_t PIER;
	volatile uint8_t WDR;
	volatile uint8_t FDR;
	volatile uint8_t PER;
} LED_TypeDef;

/**
* @brief PIT32 register definition
*/
typedef struct
{
	/*!< PIT0 base address: 0x40007000. */
	/*!< PIT1 base address: 0x40008000. */
	__IO uint32_t PCSR;  /*!< PIT control and status register.                Address offset: 0x00*/
	__IO uint32_t PMR;   /*!< PIT modulus register.                           Address offset: 0x04*/
	__IO uint32_t PCNTR; /*!< PIT count register.                             Address offset: 0x08*/
} PIT32_TypeDef;

/**
* @brief PWM Registers
*/
typedef struct
{
	/*!< PWM base address: 0x40018000*/
	__IO uint32_t PPR;    /*!< PWM Prescale divider register.                   Address offset: 0x00*/
	__IO uint32_t PDZR1;  /**< PWM DZ Register                                  Address offset: 0x04*/
	__IO uint32_t PCSR;   /**< PWM Clock Select Register                        Address offset: 0x08*/
	__IO uint32_t PCR;    /**< PWM Control Register                             Address offset: 0x0C*/
	__IO uint32_t PCR1;   /**< PWM Control Register 1                           Address offset: 0x10*/
	__IO uint32_t PCNR0;  /**< PWM Counter Register0                            Address offset: 0x14*/
	__IO uint32_t PCMR0;  /**< PWM Comparator Register0                         Address offset: 0x18*/
	__IO uint32_t PTR0;   /**< PWM Timer Register0                              Address offset: 0x1C*/
	__IO uint32_t PCNR1;  /**< PWM Counter Register1                            Address offset: 0x20*/
	__IO uint32_t PCMR1;  /**< PWM Comparator Register1                         Address offset: 0x24*/
	__IO uint32_t PTR1;   /**< PWM Timer Register1                              Address offset: 0x28*/
	__IO uint32_t PCNR2;  /**< PWM Counter Register2                            Address offset: 0x2C*/
	__IO uint32_t PCMR2;  /**< PWM Comparator Register2                         Address offset: 0x30*/
	__IO uint32_t PTR2;   /**< PWM Timer Register2                              Address offset: 0x34*/
	__IO uint32_t PCNR3;  /**< PWM Counter Register3                            Address offset: 0x38*/
	__IO uint32_t PCMR3;  /**< PWM Comparator Register3                         Address offset: 0x3C*/
	__IO uint32_t PTR3;   /**< PWM Timer Register3                              Address offset: 0x40*/
	__IO uint32_t PIER;   /**< PWM Interrupt Enable Register                    Address offset: 0x44*/
	__IO uint32_t PIFR;   /**< PWM Interrupt FlagRegister                       Address offset: 0x48*/
	__IO uint32_t PCCR0;  /**< PWM Capture Control Register0                    Address offset: 0x4C*/
	__IO uint32_t PCCR1;  /**< PWM Capture Control Register1                    Address offset: 0x50*/
	__IO uint32_t PCCR2;  /**< PWM Capture Control Register2                    Address offset: 0x54*/
	__IO uint32_t PCCR3;  /**< PWM Capture Control Register3                    Address offset: 0x58*/
	__IO uint32_t PCRLR0; /**< PWM Capture Rising Latch Register0               Address offset: 0x5C*/
	__IO uint32_t PCFLR0; /**< PWM Capture Falling Latch Register0              Address offset: 0x60*/
	__IO uint32_t PCRLR1; /**< PWM Capture Rising Latch Register1               Address offset: 0x64*/
	__IO uint32_t PCFLR1; /**< PWM Capture Falling Latch Register1              Address offset: 0x68*/
	__IO uint32_t PCRLR2; /**< PWM Capture Rising Latch Register2               Address offset: 0x6C*/
	__IO uint32_t PCFLR2; /**< PWM Capture Falling Latch Register2              Address offset: 0x70*/
	__IO uint32_t PCRLR3; /**< PWM Capture Rising Latch Register3               Address offset: 0x74*/
	__IO uint32_t PCFLR3; /**< PWM Capture Falling Latch Register3              Address offset: 0x78*/
	__IO uint32_t PPCR;   /**< PWM Port Control Register                        Address offset: 0x7C*/
	__IO uint32_t RSVD1;  /**<  reserved                                        Address offset: 0x80*/
	__IO uint32_t RSVD2;  /**<  reserved                                        Address offset: 0x84*/
	__IO uint32_t PDCR0;  /**< PWM Delay Count Register0                        Address offset: 0x88*/
	__IO uint32_t PDCR1;  /**< PWM Delay Count Register1                        Address offset: 0x8C*/
	__IO uint32_t PDCR2;  /**< PWM Delay Count Register2                        Address offset: 0x90*/
	__IO uint32_t PDCR3;  /**< PWM Delay Count Register3                        Address offset: 0x94*/
	__IO uint32_t PDCR4;  /**< PWM Delay Count Register4                        Address offset: 0x98*/
	__IO uint32_t PDCR5;  /**< PWM Delay Count Register5                        Address offset: 0x9C*/
	__IO uint32_t PDCR6;  /**< PWM Delay Count Register6                        Address offset: 0xA0*/
	__IO uint32_t PDCR7;  /**< PWM Delay Count Register7                        Address offset: 0xA4*/
	__IO uint32_t PDER;   /**< PWM Delay Enable Register                        Address offset: 0xA8*/
	__IO uint32_t RSVD3;  /**< reserved                                         Address offset: 0xAC*/
	__IO uint32_t RSVD4;  /**< reserved                                         Address offset: 0xB0*/
	__IO uint32_t RSVD5;  /**< reserved                                         Address offset: 0xB4*/
	__IO uint32_t RSVD6;  /**< reserved                                         Address offset: 0xB8*/
	__IO uint32_t RSVD7;  /**< reserved                                         Address offset: 0xBC*/
	__IO uint32_t PFPN0;  /**< PWM Fixed Pulse number Register0                 Address offset: 0xC0*/
	__IO uint32_t PFPN1;  /**< PWM Fixed Pulse number Register1                 Address offset: 0xC4*/
	__IO uint32_t PFPN2;  /**< PWM Fixed Pulse number Register2                 Address offset: 0xC8*/
	__IO uint32_t PFPN3;  /**< PWM Fixed Pulse number Register3                 Address offset: 0xCC*/
	__IO uint32_t PFPN4;  /**< PWM Fixed Pulse number Register4                 Address offset: 0xD0*/
	__IO uint32_t PFPN5;  /**< PWM Fixed Pulse number Register5                 Address offset: 0xD4*/
	__IO uint32_t PFPN6;  /**< PWM Fixed Pulse number Register6                 Address offset: 0xD8*/
	__IO uint32_t PFPN7;  /**< PWM Fixed Pulse number Register7                 Address offset: 0xDC*/
	__IO uint32_t PFPM;   /**< PWM Fixed pulse number mode Register             Address offset: 0xE0*/

} PWM_TypeDef;

/**
* @brief PWM Registers
*/
typedef struct
{
	__IO uint32_t CR1;    /*!< 0x00 PWM_TIMER control register 1               */
	__IO uint32_t CR2;    /*!< 0x04 PWM_TIMER control register 2               */
	__IO uint32_t SMCR;   /*!< 0x08 PWM_TIMER slave mode ontrol register       */
	__IO uint32_t DIER;   /*!< 0x0C PWM_TIMER DMA/interrupt enable register    */
	__IO uint32_t SR;     /*!< 0x10 PWM_TIMER status register                  */
	__IO uint32_t EGR;    /*!< 0x14 PWM_TIMER event generation register        */
	__IO uint32_t CCMR1;  /*!< 0x18 PWM_TIMER capture/compare mode register 1  */
	__IO uint32_t CCMR2;  /*!< 0x1C PWM_TIMER capture/compare mode register 2  */
	__IO uint32_t CCER;   /*!< 0x20 PWM_TIMER capture/compare enable register  */
	__IO uint32_t CNT;    /*!< 0x24 PWM_TIMER counter register                 */
	__IO uint32_t PSC;    /*!< 0x28 PWM_TIMER prescaler register               */
	__IO uint32_t ARR;    /*!< 0x2C PWM_TIMER Auto-reload value register       */
	__IO uint32_t RCR;    /*!< 0x30 PWM_TIMER repetition counter register      */
	__IO uint32_t CCR1;   /*!< 0x34 PWM_TIMER capture/compare register 1       */
	__IO uint32_t CCR2;   /*!< 0x38 PWM_TIMER capture/compare register 2       */
	__IO uint32_t CCR3;   /*!< 0x3C PWM_TIMER capture/compare register 3       */
	__IO uint32_t CCR4;   /*!< 0x40 PWM_TIMER capture/compare register 4       */
	__IO uint32_t BDTR;   /*!< 0x44 PWM_TIMER break and dead-time register     */
	__IO uint32_t DCR;    /*!< 0x48 reserved                                   */
	__IO uint32_t DMAR;   /*!< 0x4C reserved                                   */
	__IO uint32_t PMCR1;  /*!< 0x50 PWM_TIMER PWM mode ceil register 1         */
	__IO uint32_t PMCR2;  /*!< 0x54 PWM_TIMER PWM mode ceil register 2         */
	__IO uint32_t PMCR3;  /*!< 0x58 PWM_TIMER PWM mode ceil register 3         */
	__IO uint32_t PMCR4;  /*!< 0x5C PWM_TIMER PWM mode ceil register 4         */
	__IO uint32_t PMCREN; /*!< 0x60 PWM_TIMER PMCR enable register             */
	__IO uint32_t PUE;    /*!< 0x64 PWM_TIMER pull enable register             */
} PWMT_TypeDef;

/**
* @brief  RESET register definition
*/
typedef struct
{
	/*!< RESET base address: 0x40002000. */
	__IO uint32_t RCR;          /*!< RESET reset control register.               Address offset: 0x00*/
			 uint8_t  RESERVED1;    /*!< RESERVED1.                                  Address offset: 0x04*/
			 uint8_t  RESERVED2;    /*!< RESERVED2.                                  Address offset: 0x05*/
	__IO uint8_t  RTR;          /*!< RESET reset test register.                  Address offset: 0x06*/
	__IO uint8_t  RSR;          /*!< RESET reset status register.                Address offset: 0x07*/
} RESET_TypeDef;

/**
* @brief  SECURE DETECT register definition
*/
typedef struct
{
	__IO uint32_t TS1CR;   //0x00
	__IO uint32_t TS1SR;   //0x04
	__IO uint32_t MSCR;    //0x08
	__IO uint32_t OBTCR1;  //0x0c
	__IO uint32_t OBTCR2;  //0x10
	__IO uint32_t OBTCR;   //0x14
	__IO uint32_t OBTSR;   //0x18
	__IO uint32_t LFTR;    //0x1c
	__IO uint32_t HFTR;    //0x20
	__IO uint32_t OBTDR;   //0x24
	__IO uint32_t OBTCNTR; //0x28
} SECDET_TypeDef;

/**
* @brief SPI register definition
*/
typedef struct
{
	/*!< SPI1 base address: 0x4001000. */
	__IO uint8_t BR;           /*!< SPI baudrate seclection register.                        Address offset: 0x00*/
	__IO uint8_t FR;           /*!< SPI frame setting register.                              Address offset: 0x01*/
	__IO uint8_t CR1;          /*!< SPI control register1.                                   Address offset: 0x02*/
	__IO uint8_t CR2;          /*!< SPI control register2.                                   Address offset: 0x03*/
	__IO uint8_t RXFTOCTR;     /*!< SPI receive fifo timeout count register.                 Address offset: 0x04*/
	__IO uint8_t TXFTOCTR;     /*!< SPI send fifo timeout count register.                    Address offset: 0x05*/
	__IO uint8_t RXFCR;	       /*!< SPI receive fifo control register.                       Address offset: 0x06*/
	__IO uint8_t TXFCR;	       /*!< SPI send fifo control register.                          Address offset: 0x07*/
	__IO uint8_t ASCDR;        /*!< SPI sck post-delay register.                             Address offset: 0x08*/
	__IO uint8_t BSCDR;        /*!< SPI sck pre-delay register.                              Address offset: 0x09*/
	__IO uint8_t DDR;	         /*!< SPI port data direction register.                        Address offset: 0x0A*/
	__IO uint8_t PURD;	       /*!< SPI pullup and low driver register.                      Address offset: 0x0B*/
	__IO uint8_t TCNTM;        /*!< SPI transfer count low address register.                 Address offset: 0x0C*/
	__IO uint8_t TCNTH;        /*!< SPI transfer count high address register.                Address offset: 0x0D*/
	__IO uint8_t PORT;         /*!< SPI port data register.                                  Address offset: 0x0E*/
	__IO uint8_t TCNTL;        /*!< SPI TCNTL register.                                      Address offset: 0x0F*/
	__IO uint8_t IRSP;         /*!< SPI port interrupt register.                             Address offset: 0x10*/
			 uint8_t RESERVED0;    /*!< RESERVED0.                                               Address offset: 0x11*/
	__IO uint8_t DR;           /*!< SPI data low address register.                           Address offset: 0x12*/
	__IO uint8_t DRH;          /*!< SPI data high address register.                          Address offset: 0x13*/
	__IO uint8_t RXFSR;        /*!< SPI receive fifo status register.                        Address offset: 0x14*/
	__IO uint8_t TXFSR;        /*!< SPI send fifo status register.                           Address offset: 0x15*/
	__IO uint8_t SR;           /*!< SPI status high address register.                        Address offset: 0x16*/
	__IO uint8_t SRH;          /*!< SPI status low address register.                         Address offset: 0x17*/
	__IO uint8_t FDCR;         /*!< SPI fifo debug control register.                         Address offset: 0x18*/
	__IO uint8_t ICR;          /*!< SPI interrupt control register.                          Address offset: 0x19*/
	__IO uint8_t DMACR;        /*!< SPI DMA control register.                                Address offset: 0x1A*/
	__IO uint8_t DMATHR;       /*!< SPI DMA threshold register.                              Address offset: 0x1B*/
	__IO uint8_t RXFDBGR;      /*!< SPI receive fifo debug register.                         Address offset: 0x1C*/
			 uint8_t RESERVED1;    /**< RESERVED1.                                               Address offset: 0x1d*/
	__IO uint8_t TXFDBGR;      /**< SPI TXFDBGR register.                                    Address offset: 0x1e*/
			 uint8_t RESERVED3;    /*!< RESERVED3.                                               Address offset: 0x1f*/
	__IO uint8_t SPICFGDATA;   /**< SPI TXFDBGR register.                                    Address offset: 0x20*/
} SPI_TypeDef;

/**
* @brief SSI
*/
typedef struct
{
	/*!< SSI1 base address: 0x60000000. */
	__IO uint32_t CTRLR0;    	    /*!< SSI control register0.                               Address offset: 0x00*/
	__IO uint32_t CTRLR1;    	    /*!< SSI control register1.                               Address offset: 0x04*/
	__IO uint32_t SSIENR;   	    /*!< SSI enable  register.                                Address offset: 0x08*/
	__IO uint32_t MWCR;      	    /*!< SSI microwave register.                              Address offset: 0x0C*/
	__IO uint32_t SER;       	    /*!< SSI slace seclection register.                       Address offset: 0x10*/
	__IO uint32_t BAUDR;     	    /*!< SSI baud rate register.                              Address offset: 0x14*/
	__IO uint32_t TXFTLR;    	    /*!< SSI send fifo threshold register.                    Address offset: 0x18*/
	__IO uint32_t RXFTLR;    	    /*!< SSI receive fifo threshold register.                 Address offset: 0x1C*/
	__IO uint32_t TXFLR;     	    /*!< SSI send fifo level register.                        Address offset: 0x20*/
	__IO uint32_t RXFLR;     	    /*!< SSI receive fifo level register.                     Address offset: 0x24*/
	__IO uint32_t SR;        	    /*!< SSI status register.                                 Address offset: 0x28*/
	__IO uint32_t IMR;        	  /*!< SSI mask register.                                   Address offset: 0x2c*/
	__IO uint32_t ISR;        	  /*!< SSI interrupt status register.                       Address offset: 0x30*/
	__IO uint32_t RISR;       	  /*!< SSI raw interrupt state register.                    Address offset: 0x34*/
	__IO uint32_t TXOICR;         /*!< SSI send fifo overflow interrupt clean register.     Address offset: 0x38*/
	__IO uint32_t RXOICR;         /*!< SSI receive fifo overflow interrupt clean register.  Address offset: 0x3C*/	
	__IO uint32_t RXUICR;         /*!< SSI send fifo low overflow interrupt clean register. Address offset: 0x40*/
			 uint32_t RESERVED0;      /*!< RESERVED0                                            Address offset: 0x44*/
	__IO uint32_t ICR;            /*!< SSI interrupt clean register.                        Address offset: 0x48*/ 
	__IO uint32_t DMACR;          /*!< SSI DMA control register.                            Address offset: 0x4C*/
	__IO uint32_t DMATDLR;        /*!< SSI DMA send fifo data level register.               Address offset: 0x50*/
	__IO uint32_t DMARDLR;        /*!< SSI DMA receive fifo data level register.            Address offset: 0x54*/  
			 uint32_t RESERVED1[1];   /*!< RESERVED1[1].                                        Address offset: 0x58*/
	__IO uint32_t DR;             /*!< SSI data register.                                   Address offset: 0x60*/
			 uint32_t RESERVED2[35];  /*!< SSI RESERVED3[35].  addr: 0x64-0xec                  Address offset: 0x64*/
	__IO uint32_t RXSDR;          /*!< SSI sample delay register.                           Address offset: 0xf0*/
	__IO uint32_t SPICTRLR0;      /*!< SSI SPI control register.                            Address offset: 0xF4*/
			 uint32_t RESERVED3;      /*!< RESERVED4.                                           Address offset: 0xF8*/
	__IO uint32_t XIPMBR;         /*!< SSI XIP mode register.                               Address offset: 0xFC*/ 
	__IO uint32_t XIPIIR;         /*!< SSI XIP command register.                            Address offset: 0x100*/
	__IO uint32_t XIPWIR;         /*!< SSI XIP loop command register.                       Address offset: 0x104*/
	__IO uint32_t XIPCR;          /*!< SSI XIP control register.                            Address offset: 0x108*/
	__IO uint32_t XIPSER;         /*!< SSI XIP slave enable register.                       Address offset: 0x10C*/
	__IO uint32_t XRXIOCR;        /*!< SSI register.                                        Address offset: 0x110*/	
			 uint32_t RESERVED4;      /*!< RESERVED5.                                           Address offset: 0x114*/	
} SSI_TypeDef;

/**
* @brief  TC register address
*/
typedef struct
{
	/*!< TC base address: 0x40006000. */
	__IO uint16_t CR;             /*!< TC control register.         Address offset: 0x00*/
	__IO uint16_t MR;             /*!< TC modulus register.         Address offset: 0x02*/
	__IO uint16_t CNTR;           /*!< TC time count register.      Address offset: 0x04*/
	__IO uint16_t SR;             /*!< TC timer service register.   Address offset: 0x06*/
} TC_TypeDef;

 /**
 * @brief  TRNG register address
 */
 typedef struct
 {
	 	/*!< TRNG base address: 0x14000000. */
// 	__IO uint32_t CTRL;          /**< 00*/
// 	__IO uint32_t DR;            /**< 04*/
// 	__IO uint32_t TMCTRL;        /**< 08*/
// 	__IO uint32_t STSCR;         /**< 0C*/
// 	__IO uint32_t OSCR_Mx[4];    /**< 10 14 18 1C*/
// 	     uint32_t RESERVED0[10]; /**< 20 24 28 2C 30 24 38 3C 40 44*/
// 	__IO uint32_t SM3DRx[8];     /**< 48 4C 50 54 58 5C 60 64 */
// 	__IO uint32_t OSCTRIMR1;     /**< 68*/
// 	__IO uint32_t OSCTRIMR2;     /**< 6C*/
// 	__IO uint32_t OSCCTR;        /**< 70*/
// 	__IO uint32_t OSCDIVR;       /**< 74*/
	 
		__IO uint32_t CTRL;          /*!< Address offset: 0x00*/
		__IO uint32_t STAT;          /*!< Address offset: 0x04*/
		__IO uint32_t MODE;          /*!< Address offset: 0x08*/
	 	__IO uint32_t SMODE;         /*!< Address offset: 0x0C*/
	 	__IO uint32_t IE;            /*!< Address offset: 0x10*/
	 	__IO uint32_t ISTAT;         /*!< Address offset: 0x14*/
	 	__IO uint32_t RESERVED0;     /*!< Address offset: 0x18*/
	 	__IO uint32_t FEATURES;      /*!< Address offset: 0x1C*/
	 	__IO uint32_t RAND0;         /*!< Address offset: 0x20*/
	 	__IO uint32_t RAND1;     		 /*!< Address offset: 0x24*/
	 	__IO uint32_t RAND2;         /*!< Address offset: 0x28*/
	 	__IO uint32_t RAND3;         /*!< Address offset: 0x2C*/
	 	__IO uint32_t RAND4;         /*!< Address offset: 0x30*/
	 	__IO uint32_t RAND5;         /*!< Address offset: 0x34*/	
	 	__IO uint32_t RAND6;         /*!< Address offset: 0x38*/
	 	__IO uint32_t RAND7;         /*!< Address offset: 0x3C*/				 
	 
 } TRNG_TypeDef;

/**
* @brief UART register address
*/
typedef struct
{
	/*!< UART1 base address: 0x40013000. */ 
	/*!< UART2 base address: 0x40014000. */
	/*!< UART3 base address: 0x4001d000. */
	__IO uint8_t BDL;            /*!< UART baudrate low address register.                      Address offset: 0x00*/
	__IO uint8_t BDH;            /*!< UART baudrate high address register.                     Address offset: 0x01*/
	__IO uint8_t CR2;            /*!< UART control register2.                                  Address offset: 0x02*/
	__IO uint8_t CR1;            /*!< UART control register1.                                  Address offset: 0x03*/
	__IO uint8_t SR2;            /*!< UART status register2.                                   Address offset: 0x04*/
	__IO uint8_t SR1;            /*!< UART status register1.                                   Address offset: 0x05*/
	__IO uint8_t DRL;            /*!< UART data low address register.                          Address offset: 0x06*/
	__IO uint8_t DRH;            /*!< UART data high register.                                 Address offset: 0x07*/
	__IO uint8_t PORT;           /*!< UART port data register.                                 Address offset: 0x08*/
	__IO uint8_t PURD;           /*!< UART pullup and driver register.                         Address offset: 0x09*/
	__IO uint8_t BRDF;           /*!< UART decimal fraction baudrate register.                 Address offset: 0x0A*/
	__IO uint8_t DDR;            /*!< UART data direction register.                            Address offset: 0x0B*/
	__IO uint8_t IRCR;           /*!< UART infrared control register.                          Address offset: 0x0C*/
	__IO uint8_t TR;             /*!< UART test register.                                      Address offset: 0x0D*/
	__IO uint8_t FCR;            /*!< UART fifo control register.                              Address offset: 0x0E*/
	__IO uint8_t IRDR;           /*!< UART infrared divider register.                          Address offset: 0x0F*/
	__IO uint8_t DCR;            /*!< UART DMA control register.                               Address offset: 0x10*/
	__IO uint8_t FSR;            /*!< UART fifo status register.                               Address offset: 0x11*/
	__IO uint8_t RXTOCTR;        /*!< UART receive fifo timeout register.                      Address offset: 0x12*/
	__IO uint8_t FCR2;           /*!< UART fifo control register2.                             Address offset: 0x13*/
	__IO uint8_t FCTRL;          /*!< UART flow control register.                              Address offset: 0x14*/
	__IO uint8_t FSR2;           /*!< UART status register2.                                   Address offset: 0x15*/

} UART_TypeDef;

/**
* @brief WDT register address
*/
typedef struct
{
	/*!< WDT base address: 0x40005000. */
	__IO uint16_t WCR;    /*!< WDT control register.             Address offset: 0x00*/
	__IO uint16_t WMR;    /*!< WDT modulus register.             Address offset: 0x02*/
	__IO uint16_t WCNTR;  /*!< WDT count register.               Address offset: 0x04*/
	__IO uint16_t WSR;    /*!< WDT service register.             Address offset: 0x06*/
} WDT_TypeDef;


#ifdef __cplusplus
}
#endif

#endif /* __CCM4202S_REG_H */

/************************ (C) COPYRIGHT C*Core *****END OF FILE*************/
